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Hi,guys:
I have a high speed (2.5G)digital signal with timing jitter,now I want to see the eyediagram.I have monitor the signal ,but how can I get it's eyediagram?
Anyone can help me ?
Thank you...
The "clk" came from analog behavior model with multi_driver....Maybe the problem is from there.But now I could not rewrite the analog behavior model ,is there any method to remove the "0" width pulse?
Hi,guys:
when I wrote a simple alway block,the 0 width pulse problem came out..
always@(posedge clk) begin
a = $random;
end
always@(negedge clk) begin
b = $random;
end
But saw the waveform ,I found that the sometimes a and b changed at the same time.There is a "0" width pulse in...
Thanks for your reply.I tried as you said except using "=" instead of "<=",because I need the begin....end block exeute sequently.But the result is the same as before......
A verilog behavior model problem....
Hi,guys:
I want to add jitter to a signal clk.When using random generator task,I need integer data as seed in always block like this:
integer seed;
real d;
always begin
@(posedge clk);
seed = $random;
d = $dist_normal(seed,0,1)/1000.0;
# d ...
Hi,guys:
I need to use $dist_normal to generate random data.The task $dist_normal has 3 parameters:SEED,MEAN,STDEV.I only want to maks sure the MEAN and STDEV,the SEED is random.
How can i use the first parameter of task $dist_normal(????,DATA1,DATA2)?
Anyone can help me ?
Thanks
Thank you for your reply.
After tracing the "x' ,I find it is not from timing violation,but from the beginning "x" which should not spread.For example:A0=0,A1=x_logic,B0=x_logic,B1=1.A1 and B0 connect to the same signal.
The output Y= ~(A0|A1) | (B0&B1).If x_logic is "x" ,Y will be "x".But in...
Hi,guys!
I am running post simulation now and confused in gate level "x" state which is not exist in RTL simulation.Tracing "x" is not a good job .Anyone can give any suggestion on deal with the "x"?ignore or fixed them ?
Thank you for your reply,yang.
as you say, I think most "x" came from registers without reset or behavioral models without initial value.
To fix them, now,my only choice that I can chose is to force the signal one by one.I want to kown ,is there better method to deal with it?
guide me please!
Hi all,
When i use vcs to simulate a design with behavioral models,some "x" or "z" state found especially some read only registers.How should I deal with them more effectively?Because there are too many....anyone can guide me ?
thanks
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