The difference of RTL and gate simulation ?

[rettylee]

Hi,guys!
I am running post simulation now and confused in gate level "x" state which is not exist in RTL simulation.Tracing "x" is not a good job .Anyone can give any suggestion on deal with the "x"?ignore or fixed them ?

 

[ljxpjpjljx]

you should trace X in gate level simulation to boot up the whole system!
you should analyze the root cause of x status!

 

[rettylee]

Thank you for your reply.
After tracing the "x' ,I find it is not from timing violation,but from the beginning "x" which should not spread.For example:A0=0,A1=x_logic,B0=x_logic,B1=1.A1 and B0 connect to the same signal.
The output Y= ~(A0|A1) | (B0&B1).If x_logic is "x" ,Y will be "x".But in fact,Y= x_logc | (~x_logic) = 1 all the time in boolean.......
and in counter,when counter[0] encouter "x",the "x" will spread too.But in fact ,I don't care it is "0" or "1".....
How should I deal with such condition?
Thanks for your example,pini_1.I will see that later.