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Recent content by replyanil

  1. R

    Problem with CMOS inverter (power supply issues)

    Re: cmos inverter that means you says supply is 3.3v and input is 5v then what happens if it will connects i think there nothing will b happened as some threshold voltage drop will get across nmos
  2. R

    Opinions on All-Digital PLL design

    All Digital PLL dpll is good as cmpre to aother pll (spll,lpll.adpll)
  3. R

    How to simulate ring oscillator with 3 inverters?

    Ring oscillator do care size of width and length and supply
  4. R

    What is the best book for learning CMOS Opamps?

    Re: CMOS Opamps chein its autor name i m not remember book name baker by cmos vlsi design allen razavi
  5. R

    what is hot topics in analog design research?

    i think lna amplifier,pll, power amp,vco design
  6. R

    What are the effects of dividing the VCO output by 2 on output jitter?

    Re: about jiiter that depends which kind of vco likely to be desigh actually lc vco is having less jitter compare to ring vco
  7. R

    CMOS model needed urgently

    you can get from ptm(predictive technology model)
  8. R

    Opinions on All-Digital PLL design

    digital pll sampling rate dpll is the best of all spll,adpll.apll while design point of view its having high q, low phase noise if u consider lc vco rather than other vco
  9. R

    A Versatile Low-Jitter PLL in 90-nm CMOS for SerDes Transmitter Clocking

    it is digital phase locked loop paper on 90 nm technolgy
  10. R

    those who want to work on ads

    it is a very simple way to work on ads.those who are a starter having a very good kind of platform.
  11. R

    ADS , creating a hierarchy

    i did the same way but couldn't happened

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