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Recent content by renuvamsi

  1. R

    Help in Synthesis using DC compiler

    Hello , I have a question in synthesis process . This is the process i am doing :: analyze -f verilog xyz.v elaborate xyz set_max_area 0 compile report_timing Point Incr Path -----------------------------------------------------------...
  2. R

    Need urgent help ...verilog code error

    thanq so much for ur help !!! I finally got the output :-) i will be luking forward for ur help in future
  3. R

    Need urgent help ...verilog code error

    `timescale 1ns/1ns module reg_test(); reg clk,ena,rst; reg [7:0]data; wire [7:0]reg_out; register uut(reg_out,data,ena,clk,rst); initial begin clk=1'b0; forever #20 clk=~clk; end initial begin rst=1'b0; #40 data=8'hA3;ena=1'b1;rst=1'b1; #40 ena=1'b1;data=8'h15; #40 ena=1'b0; #40...
  4. R

    Need urgent help ...verilog code error

    No i cam getting the same error ...... May be there is something wrong in regmux module. In NC sim , i got that error
  5. R

    Need urgent help ...verilog code error

    Hello , I am new to verilog ...can someone help me urgent .. I have a task for 8 bit register where in i have to model hierarchial modeling ....... here are my modules .... correct me please Someone please patietnly go through all modules and let me know whas wrong in it .... `timescale...
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