Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Help in Synthesis using DC compiler

Status
Not open for further replies.
R

renuvamsi

Newbie level 4
Newbie level 4
Joined
Sep 9, 2008
Messages
5
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,405
Hello ,

I have a question in synthesis process . This is the process i am doing ::
analyze -f verilog xyz.v
elaborate xyz
set_max_area 0
compile
report_timing
Point Incr Path
-----------------------------------------------------------
INS1/OUT_reg[0]/CP (FD1) 0.00 0.00 r
INS1/OUT_reg[0]/Q (FD1) 1.47 1.47 f
INS1/OUT[0] (SOP_width16_0) 0.00 1.47 f
OUT1[0] (out) 0.00 1.47 f
data arrival time 1.47
-----------------------------------------------------------
(Path is unconstrained)

thee is some data arrival time ...where does that come from ??????????

this is th report i am getting
then after setting timing constraints
create_clock CLK -period 40.1
without re-compiling , i am viewing the reports and i got the below report


Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
input external delay 0.00 0.00 f
B1[2] (in) 0.00 0.00 f
INS1/B[2] (SOP_width16_0) 0.00 0.00 f
INS1/r57/B[2] (SOP_width16_0_DW02_mult_0) 0.00 0.00 f
INS1/r57/U47/Z (IVP) 1.40 1.40 r
INS1/r57/U230/Z (NR2) 0.43 1.83 f
INS1/r57/U81/Z (AN2P) 0.91 2.74 f
INS1/r57/S2_2_2/CO (FA1A) 2.27 5.01 f
INS1/r57/S2_3_2/CO (FA1A) 2.27 7.29 f
INS1/r57/S2_4_2/CO (FA1A) 2.27 9.56 f
INS1/r57/S2_5_2/CO (FA1A) 2.27 11.84 f
INS1/r57/S2_6_2/CO (FA1A) 2.27 14.11 f
INS1/r57/S2_7_2/CO (FA1A) 2.27 16.38 f
INS1/r57/S2_8_2/CO (FA1A) 2.27 18.66 f
INS1/r57/S2_9_2/CO (FA1A) 2.27 20.93 f
INS1/r57/S2_10_2/CO (FA1A) 2.27 23.21 f
INS1/r57/S2_11_2/CO (FA1A) 2.27 25.48 f
INS1/r57/S2_12_2/CO (FA1A) 2.27 27.75 f
INS1/r57/S2_13_2/CO (FA1A) 2.27 30.03 f
INS1/r57/S2_14_2/CO (FA1A) 2.27 32.30 f
INS1/r57/S4_2/CO (FA1A) 2.34 34.64 f
INS1/r57/U6/Z (EO) 1.19 35.83 f
INS1/r57/FS_1/A[16] (SOP_width16_0_DW01_add_1) 0.00 35.83 f
INS1/r57/FS_1/U83/Z (NR2) 1.33 37.16 r
INS1/r57/FS_1/U4/Z (IVP) 0.19 37.35 f
INS1/r57/FS_1/U77/Z (AO6) 1.60 38.95 r
INS1/r57/FS_1/U76/Z (EN) 1.26 40.21 f
INS1/r57/FS_1/SUM[17] (SOP_width16_0_DW01_add_1) 0.00 40.21 f
INS1/r57/PRODUCT[19] (SOP_width16_0_DW02_mult_0) 0.00 40.21 f
INS1/add_22/B[19] (SOP_width16_0_DW01_add_0) 0.00 40.21 f
INS1/add_22/U1_19/CO (FA1A) 2.27 42.48 f
INS1/add_22/U1_20/CO (FA1A) 1.17 43.66 f
INS1/add_22/U1_21/CO (FA1A) 1.17 44.83 f
INS1/add_22/U1_22/CO (FA1A) 1.17 46.01 f
INS1/add_22/U1_23/CO (FA1A) 1.17 47.18 f
INS1/add_22/U1_24/CO (FA1A) 1.17 48.35 f
INS1/add_22/U1_25/CO (FA1A) 1.17 49.53 f
INS1/add_22/U1_26/CO (FA1A) 1.17 50.70 f
INS1/add_22/U1_27/CO (FA1A) 1.17 51.88 f
INS1/add_22/U1_28/CO (FA1A) 1.17 53.05 f
INS1/add_22/U1_29/CO (FA1A) 1.17 54.22 f
INS1/add_22/U1_30/CO (FA1A) 1.17 55.40 f
INS1/add_22/U1_31/Z (EO3P) 1.99 57.39 f
INS1/add_22/SUM[31] (SOP_width16_0_DW01_add_0) 0.00 57.39 f
INS1/U67/Z (AO2) 1.08 58.47 r
INS1/U66/Z (AO7) 0.45 58.92 f
INS1/OUT_reg[31]/D (FD1) 0.00 58.92 f
data arrival time 58.92

clock CLK (rise edge) 40.10 40.10
clock network delay (ideal) 0.00 40.10
INS1/OUT_reg[31]/CP (FD1) 0.00 40.10 r
library setup time -0.80 39.30
data required time 39.30
--------------------------------------------------------------------------
data required time 39.30
data arrival time -58.92
--------------------------------------------------------------------------
slack (VIOLATED) -19.62


now , i compiled it with the same time constraint

Point Incr Path
--------------------------------------------------------------------------
clock (input port clock) (rise edge) 0.00 0.00
input external delay 0.00 0.00 r
A1[14] (in) 0.00 0.00 r
INS1/DP_OP_6J1_296_2454/U1140/Z (EN) 3.71 3.71 r
U5/Z (ND2) 1.67 5.37 f
INS1/DP_OP_6J1_296_2454/U881/Z (AO4) 1.70 7.08 r
INS1/DP_OP_6J1_296_2454/U792/S (HA1) 1.22 8.30 r
INS1/DP_OP_6J1_296_2454/U789/S (FA1A) 2.14 10.44 r
INS1/DP_OP_6J1_296_2454/U787/S (FA1A) 2.28 12.72 r
INS1/DP_OP_6J1_296_2454/U786/S (FA1A) 1.33 14.05 r
U309/Z (AN2P) 0.83 14.87 r
INS1/DP_OP_6J1_296_2454/U579/Z (MUX21L) 0.58 15.45 f
INS1/DP_OP_6J1_296_2454/U567/Z (MUX21L) 0.89 16.34 r
INS1/DP_OP_6J1_296_2454/U563/Z (MUX21L) 0.68 17.03 f
U368/Z (IVP) 0.69 17.71 r
INS1/DP_OP_6J1_296_2454/U553/Z (EN) 1.26 18.97 f
INS1/DP_OP_6J1_296_2454/U200/Z (NR2) 1.33 20.30 r
INS1/DP_OP_6J1_296_2454/U197/Z (AO7) 0.45 20.75 f
INS1/DP_OP_6J1_296_2454/U195/Z (AO6) 1.08 21.83 r
U374/Z (IV) 0.27 22.10 f
INS1/DP_OP_6J1_296_2454/U192/CO (FA1A) 1.17 23.27 f
INS1/DP_OP_6J1_296_2454/U191/CO (FA1A) 1.17 24.44 f
INS1/DP_OP_6J1_296_2454/U190/CO (FA1A) 1.17 25.62 f
INS1/DP_OP_6J1_296_2454/U189/CO (FA1A) 1.17 26.79 f
INS1/DP_OP_6J1_296_2454/U188/CO (FA1A) 1.17 27.97 f
INS1/DP_OP_6J1_296_2454/U187/CO (FA1A) 1.17 29.14 f
INS1/DP_OP_6J1_296_2454/U186/CO (FA1A) 1.17 30.31 f
INS1/DP_OP_6J1_296_2454/U185/CO (FA1A) 1.17 31.49 f
INS1/DP_OP_6J1_296_2454/U184/CO (FA1A) 1.17 32.66 f
INS1/DP_OP_6J1_296_2454/U183/CO (FA1A) 1.17 33.84 f
INS1/DP_OP_6J1_296_2454/U182/CO (FA1A) 1.17 35.01 f
INS1/DP_OP_6J1_296_2454/U181/CO (FA1A) 1.17 36.18 f
INS1/DP_OP_6J1_296_2454/U180/CO (FA1A) 1.11 37.29 f
INS1/DP_OP_6J1_296_2454/U178/Z (EO) 1.13 38.42 f
U597/Z (ND2) 0.64 39.05 r
INS1/OUT_reg[31]/CR (FDS2) 0.00 39.05 r
data arrival time 39.05

clock CLK (rise edge) 40.10 40.10
clock network delay (ideal) 0.00 40.10
INS1/OUT_reg[31]/CP (FDS2) 0.00 40.10 r
library setup time -0.90 39.20
data required time 39.20
--------------------------------------------------------------------------
data required time 39.20
data arrival time -39.05
--------------------------------------------------------------------------
slack (MET) 0.15

I got the meaningful report
Why is it that before setting timing constraint , I am getting a meaningless report ....and also after setting timing constraint without recompiling , still non-sensible report
Then when i compiled it , I got a sensible report ....why is it happening ????

Can some one help me with this ?? mainly about the data arrival time
 

a few things ...

1) Without timing constraints loaded DC cannot see any valid timing paths. You will always get "Path is Unconstrained" for every path in your design.

2) Load your timing constraints before your initial compile. If not you will get lots of failing paths as in your 2nd report. Again, if DC cannot see valid timing paths, it cannot optimized them, so it's almost guaranteed they will fail.

3) You showed 3 different paths at the 3 stages. Sometimes you may want to see whats happening to the same path. Do this by ...

report_timing -from <start_point> -to <endpoint>

ex.
report_timing -from B1[2] -to INS1/OUT_reg[31]/D

4) Good constraints are the most important thing for good synthesis results. Do some checks to be sure you have good coverage on your design.

Be sure all your flops are getting clocked (I think its check_design -no_clock). You can also check the other errors/warnings in check_design.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top