Need urgent help ...verilog code error

[renuvamsi]

Hello ,
I am new to verilog ...can someone help me urgent ..
I have a task for 8 bit register where in i have to model hierarchial modeling .......
here are my modules .... correct me please

Someone please patietnly go through all modules and let me know whas wrong in it ....


`timescale 1ns/1ns
module register(reg_out,data,ena,clk,rst);

output [7:0] reg_out;
input [7:0] data;
input ena,clk,rst;

regmux register0(reg_out[0],q,data[0],ena,clk,rst);
regmux register1(reg_out[1],q,data[1],ena,clk,rst);
regmux register2(reg_out[2],q,data[2],ena,clk,rst);
regmux register3(reg_out[3],q,data[3],ena,clk,rst);
regmux register4(reg_out[4],q,data[4],ena,clk,rst);
regmux register5(reg_out[5],q,data[5],ena,clk,rst);
regmux register6(reg_out[6],q,data[6],ena,clk,rst);
regmux register7(reg_out[7],q,data[7],ena,clk,rst);

endmodule


`timescale 1ns/1ns

module regmux(r,q,d,ena,clk,rst);

output r;
input q,d,ena,clk,rst;
wire x,qb;
MUX2to1 muxinst(x,q,d,ena);
dff dffinst(q,qb,rst,clk,x);
endmodule



`timescale 1ns/1ns

module MUX2to1(x,q,data,enable);

output x;
input q,data,enable;
wire q1,data1,enablebar;

not (enablebar,enable);
and (q1,q,enablebar);
and (data1,data,enable);
or (x,data1,q1);
endmodule
~


`timescale 1ns/1ns

module dff(q,qb,clear,clock,data);
output q,qb;
input clock,data,clear;
wire cb,clr,clkb,clk,db,d,s,sb,r,rb;

defparam SR1.x=4.8,SR2.x=4.5,SR3.x=5;
defparam SR1.y=3.3,SR2.y=4.5,SR3.y=4.5;

not #(2.3) not1(cb,clear);
not #(2.8) not2(clr,cb);
not #(2.3) not3(clkb,clock);
not #(2.5) not4(clk,clkb);
not #(2.3) not5(db,data);
not #(2.3) not6(d,db);

SR_Latch2 SR1(s,sb,clr,clk,1'b1,rb);
SR_Latch2 SR2(r,rb,clk,s,d,clr);
SR_Latch2 SR3(q,qb,1'b1,s,clr,r);

endmodule

~

`timescale 1ns/1ns

module SR_Latch2(Q,Qb,s0,s1,r0,r1);

output Q,Qb;
input s0,s1,r0,r1;

parameter x=4.5;
parameter y=4.5;

nand #(x) nand1(Q,s0,s1,Qb);
nand # nand2(Qb,r0,r1,Q);

endmodule





i am getting tthis error ....ncvlog: *E,EXPMPA (regmux.v,21|0): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
Total errors/warnings found outside modules and primitives:
errors: 1, warnings: 0
ncverilog: *E,VLGERR: An error occurred during parsing. Review the log file for errors with the code *E and fix those identified problems to proceed. Exiting with code (status 1).
..

Therre is error regmux module ..but seems to be evrything perfect ....can someone help .... Also i doubt there is soehting wrong with parameter overriding ..also need helo in it ,,,,,

Thanks
Renuka

 

[dcreddy1980]

I have just compiled the code. I don't see any error in the code. I have used NC-sim.

Except that i got :not #(2.Cool not2(clr,cb); from your code in dff module and i changed to not #(2.0) not2(clr,cb);

 

[renuvamsi]

No i cam getting the same error ......
May be there is something wrong in regmux module.
In NC sim , i got that error

 

[ljxpjpjljx]

try to use modelsim!

 

[dcreddy1980]

`timescale 1ns/1ns
module register(reg_out,data,ena,clk,rst);

output [7:0] reg_out;
input [7:0] data;
input ena,clk,rst;

regmux register0(reg_out[0],q,data[0],ena,clk,rst);
regmux register1(reg_out[1],q,data[1],ena,clk,rst);
regmux register2(reg_out[2],q,data[2],ena,clk,rst);
regmux register3(reg_out[3],q,data[3],ena,clk,rst);
regmux register4(reg_out[4],q,data[4],ena,clk,rst);
regmux register5(reg_out[5],q,data[5],ena,clk,rst);
regmux register6(reg_out[6],q,data[6],ena,clk,rst);
regmux register7(reg_out[7],q,data[7],ena,clk,rst);

endmodule


`timescale 1ns/1ns

module regmux(r,q,d,ena,clk,rst);

output r;
input q,d,ena,clk,rst;
wire x,qb;
MUX2to1 muxinst(x,q,d,ena);
dff dffinst(q,qb,rst,clk,x);
endmodule



`timescale 1ns/1ns

module MUX2to1(x,q,data,enable);

output x;
input q,data,enable;
wire q1,data1,enablebar;

not (enablebar,enable);
and (q1,q,enablebar);
and (data1,data,enable);
or (x,data1,q1);
endmodule



`timescale 1ns/1ns

module dff(q,qb,clear,clock,data);
output q,qb;
input clock,data,clear;
wire cb,clr,clkb,clk,db,d,s,sb,r,rb;

defparam SR1.x=4.8,SR2.x=4.5,SR3.x=5;
defparam SR1.y=3.3,SR2.y=4.5,SR3.y=4.5;

not #(2.3) not1(cb,clear);
not #(2.0) not2(clr,cb);
not #(2.3) not3(clkb,clock);
not #(2.5) not4(clk,clkb);
not #(2.3) not5(db,data);
not #(2.3) not6(d,db);

SR_Latch2 SR1(s,sb,clr,clk,1'b1,rb);
SR_Latch2 SR2(r,rb,clk,s,d,clr);
SR_Latch2 SR3(q,qb,1'b1,s,clr,r);

endmodule



`timescale 1ns/1ns

module SR_Latch2(Q,Qb,s0,s1,r0,r1);

output Q,Qb;
input s0,s1,r0,r1;

parameter x=4.5;
parameter y=4.5;

nand #(x) nand1(Q,s0,s1,Qb);
nand #(y) nand2(Qb,r0,r1,Q);

endmodule

I have used the above code for compilation and it works. I have used NC-sim to compile the code. Check if you have proper libraries installed because the code contains verilog primitives in it.

 

[renuvamsi]

`timescale 1ns/1ns

module reg_test();

reg clk,ena,rst;
reg [7:0]data;
wire [7:0]reg_out;

register uut(reg_out,data,ena,clk,rst);

initial
begin
clk=1'b0;
forever
#20 clk=~clk;
end

initial begin


rst=1'b0;
#40 data=8'hA3;ena=1'b1;rst=1'b1;
#40 ena=1'b1;data=8'h15;
#40 ena=1'b0;
#40 ena=1'b1;data=8'hB9;
#140 $stop;
#10 $finish;
end

initial
$monitor($time,"rst=%b clk=%b ena=%b data=%h output=%h",rst,clk,ena,data,reg_out);

endmodule



`timescale 1ns/1ns

module SR_Latch2(Q,Qb,s0,s1,r0,r1);

output Q,Qb;
input s0,s1,r0,r1;

parameter x=4.5;
parameter y=4.5;

nand #(x) nand1(Q,s0,s1,Qb);
nand # nand2(Qb,r0,r1,Q);

endmodule
~
~
`timescale 1ns/1ns

module dff(q,qb,clear,clock,data);

output q,qb;
input clock,data,clear;
wire cb,clr,clkb,clk,db,d,s,sb,r,rb;

defparam SR1.x=4.8,SR2.x=4.5,SR3.x=5.0;
defparam SR1.y=3.3,SR2.y=4.5,SR3.y=4.5;

not #(2.3) not1(cb,clear);
not #(2.8) not2(clr,cb);
not #(2.3) not3(clkb,clock);
not #(2.5) not4(clk,clkb);
not #(2.3) not5(db,data);
not #(2.3) not6(d,db);

SR_Latch2 SR1(s,sb,clr,clk,1'b1,rb);
SR_Latch2 SR2(r,rb,clk,s,d,clr);
SR_Latch2 SR3(q,qb,1'b1,s,clr,r);

endmodule


`timescale 1ns/1ns

module MUX2to1(x,r,data,enable);

output x;
input r,data,enable;
wire r1,data1,enablebar;

not #(2.3) (enablebar,enable);
and #(3.3) (r1,r,enablebar);
and #(3.3) (data1,data,enable);
or #(3.3) (x,data1,r1);

endmodule


`timescale 1ns/1ns

module regmux(r,d,ena,clk,rst);

inout r;
input d,ena,clk,rst;
wire x,qb;

MUX2to1 muxinst(x,r,d,ena);
dff dffinst(r,qb,rst,clk,x);
endmodule



`timescale 1ns/1ns

module register(reg_out,data,ena,clk,rst);

inout [7:0] reg_out;
input [7:0] data;
input ena,clk,rst;
wire [7:0] reg_out;
wire [7:0] data;



regmux register0(reg_out[0],reg_out[0],data[0],ena,clk,rst);
regmux register1(reg_out[1],reg_out[1],data[1],ena,clk,rst);
regmux register2(reg_out[2],reg_out[2],data[2],ena,clk,rst);
regmux register3(reg_out[3],reg_out[3],data[3],ena,clk,rst);
regmux register4(reg_out[4],reg_out[4],data[4],ena,clk,rst);
regmux register5(reg_out[5],reg_out[5],data[5],ena,clk,rst);
regmux register6(reg_out[6],reg_out[6],data[6],ena,clk,rst);
regmux register7(reg_out[7],reg_out[7],data[7],ena,clk,rst);

endmodule



Here are the modules and the test bench I applied for the circuit. I am getting some unwanted spikes in the output ....like ::



0rst=0 clk=0 ena=x data=xx output=xx
15rst=0 clk=0 ena=x data=xx output=00
20rst=0 clk=1 ena=x data=xx output=00
40rst=1 clk=0 ena=1 data=a3 output=00
60rst=1 clk=1 ena=1 data=a3 output=00
75rst=1 clk=1 ena=1 data=a3 output=a3
80rst=1 clk=0 ena=1 data=15 output=a3
100rst=1 clk=1 ena=1 data=15 output=a3
115rst=1 clk=1 ena=1 data=15 output=b7
120rst=1 clk=0 ena=0 data=15 output=15
140rst=1 clk=1 ena=0 data=15 output=15
160rst=1 clk=0 ena=1 data=b9 output=15
180rst=1 clk=1 ena=1 data=b9 output=15
195rst=1 clk=1 ena=1 data=b9 output=bd
200rst=1 clk=0 ena=1 data=b9 output=b9
220rst=1 clk=1 ena=1 data=b9 output=b9
240rst=1 clk=0 ena=1 data=b9 output=b9
260rst=1 clk=1 ena=1 data=b9 output=b9
280rst=1 clk=0 ena=1 data=b9 output=b9


at 115 , there is a spike of b7 also at 195 bd , which are unwanted . I can't find the mistake i am doing . This is kind of urgent ...can someone help for the output .......

I dont know where am I doing wrong ,,,,can someone check code and let me know about the code changes ....

I doubt on parameter overriding ..but not sure ....

Please help !!!!!

 

[mytechface]

Did you miss 1 port in regmux on you latest version?

module regmux(r,d,ena,clk,rst);

has 5 ports. you used to have 6. also on the instantiation of regmux, it has 6 too...

regmux register0(reg_out[0],reg_out[0],data[0],ena,clk,rst);


you might want to fix that and see if that is your problem.

 

[renuvamsi]

thanq so much for ur help !!!
I finally got the output
i will be luking forward for ur help in future