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Recent content by rekhavp

  1. R

    Warns me: Xst:2170 - Unit arbitter: signal(s) form a combinatorial loop

    Hi all While simulating a NAND latch the following warning is produced. HOW can I eliminate this? WARNING:Xst:2170 - Unit arbitter : the following signal(s) form a combinatorial loop: Q.code is also attached with it. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use...
  2. R

    iimplementation to FPGA

    Hi, I want to give the input as the testbench to the FPGA . (I dont want to give the input manualy), Is it possible?
  3. R

    iimplementation to FPGA

    Sorry for my bad English. I meant that I want to combine the VHDL RTL code and the VHDL test bench file,(presently both are in different .vhd files) in to a single file (could be any other format) to implement in FPGA . I heard that it is possible to meet the timing constraints by doing this...
  4. R

    iimplementation to FPGA

    Thanking you for your feedback.Yes, I heard that by creating a file that containing the VHDL test bench file and the RTL code manualy ,Implementation to FPGA is directly possible.Is it possible
  5. R

    iimplementation to FPGA

    I am trying to implement a VHDL code in to FPGA. Before implementation how can I combine the VHDL test bench file with the source file?
  6. R

    [Moved] cascaded mux implementation using vhdl

    cascaded mux implementation using vhdl language I have written a VHDL code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. I'm attaching the code with this.Also the...
  7. R

    [Moved] cascaded mux implementation using vhdl

    I have written a VHDL code for a number of cascaded mux stages. During simulation it is observed that the syntax is succesfull and RTL schematic is generated. But I can't implement the test bench waveform. If any one know how to fix this please help me . It is urgent. I'm attaching the code with...
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