iimplementation to FPGA

[rekhavp]

I am trying to implement a VHDL code in to FPGA. Before implementation how can I combine the VHDL test bench file with the source file?

 

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Do you mean how do you simulate your FPGA RTL code with your testbench? I don't think you want to synthesize the testbench into the FPGA with your RTL or do you?

 

[sharath666]

To combine your testbench with your source file, you have to ensure that your testbench is synthesizable. I am assuming it is some kind of a self testing setup..

 

[rekhavp]

Do you mean how do you simulate your FPGA RTL code with your testbench? I don't think you want to synthesize the testbench into the FPGA with your RTL or do you?

Thanking you for your feedback.Yes, I heard that by creating a file that containing the VHDL test bench file and the RTL code manualy ,Implementation to FPGA is directly possible.Is it possible

 

[ads-ee]

Thanking you for your feedback.Yes, I heard that by creating a file that containing the VHDL test bench file and the RTL code manualy ,Implementation to FPGA is directly possible.Is it possible

What do you mean by "Implementation to FPGA is directly possible"?

I can tell you're not fluent in English, so I'm having a hard time figuring out what you are trying to do.

Do you want to include the testbench in the FPGA implementation? As sharath66 said the testbench has to be synthesizable.

 

[rekhavp]

What do you mean by "Implementation to FPGA is directly possible"?

I can tell you're not fluent in English, so I'm having a hard time figuring out what you are trying to do.

Do you want to include the testbench in the FPGA implementation? As sharath66 said the testbench has to be synthesizable.

Sorry for my bad English. I meant that I want to combine the VHDL RTL code and the VHDL test bench file,(presently both are in different .vhd files) in to a single file (could be any other format) to implement in FPGA . I heard that it is possible to meet the timing constraints by doing this way.Can any one suggest any method??

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Sorry for my bad English. I meant that I want to combine the VHDL RTL code and the VHDL test bench file,(presently both are in different .vhd files) in to a single file (could be any other format) to implement in FPGA . I heard that it is possible to meet the timing constraints by doing this way.Can any one suggest any method??

Hi,
Actually I want to give the test bench as the input to FPGA. How is it possible?

 

[rekhavp]

Hi,
I want to give the input as the testbench to the FPGA . (I dont want to give the input manualy), Is it possible?

 

[sharath666]

It is possible. You have to write a synthesizable testbench for that. Then synthesize the RTL as well as the testbench (both enclosed in a wrapper maybe..) and generate a single bit file which will then be downloaded onto the FPGA.