Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
ok, i tried the following code..as you said,
module asg1(clk, a, out1);
input a, clk;
output out1;
reg q, out1;
wire d;
assign d = q;
always@(posedge clk)
begin
q <= q;
end
always@(a or q)
begin
out1 = (q & a);
end
endmodule
and these are the warnings i got while i tried doing the...
thats my assignment question...
i tried a lot of ways and did realize to synthesize a code for that particular code is not possible...
---------- Post added at 15:08 ---------- Previous post was at 15:07 ----------
thanks a lot 'lostinxlation'
---------- Post added at 15:36 ----------...
is it possible to declare d input that way..
i mean, it was declared as input d;
and
wire d = q;
is this possible?
if i try to synthesize in xilinx i get the following error:
Invalid use of input signal <d> as target.
lostinxlation ,
according to the circuit, a connection should exist between q output and d input. however i try, couldnt come up with a code that will synthesize.
following is a code for the circuit, except that the connection btw q and d of FF is not coded..
can you please tell me how do i...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
