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Re: Is this plot stable?
Yes, that's the part I don't understand. I attached the schematic here for reference. It's a two stage opamp. The first stage is a full differential with cascode. It has been tweaked a little bit to generate a fixed bias that the current goes through the middle two...
I'm using current steering architecture and after running corner analysis in cadence, I have a bunch of plots cluttered together at the output. I was confused on picking the one that has the worst case INL/DNL. Anybody has any suggestion?
I'm on a project to design a bandpass Gm-C filter and one of the requirement spec is Total Harmonic Distortion less than 50dB with two tone input signals at 1v peak-to-peak. As far as I know, transconductor usually has large input and output impedance. Small voltage change at the input will...
Hi, I was using cadence to simulate a fully differential cmos transconductor and I had an issue with the source signal generating run-time. Whatever run-time I set, the input sinusoidal signal will stop at about 17ms. Like in the attachment, the run-time is 20ms and finished successfully but it...
Hi everyone, I was trying to simulate the settling time of a D/A converter in cadence. Because I'm using a DAC from the AHDL library and it's an idea one, therefore the simulation result doesn't contain a settling period. I'm thinking to use a RC circuit to simulate that case but I'm not sure...
This is a two stage op amp. The first stage is a folded cascode and second stage is common source stage. I'm directly using the second stage driving the output resistance. I'm measuring the PSRR+ by connecting the output to the negative input while grounding the positive input. See the...
With a folded cascode of the first stage and common source as the second stage. How to calculate the slew rate?
The value I calculated by Itail/Cc, that is the tail current of the differential divided by compensation capacitance, is far different than the one I simulated. Should we consider...
Thank you guys for those replies. I read some materials and found a general procedure for a two stage op amp. It's based on the requirement specification for those amp parameters. I summarized the procedure as follow:
1. Choose the smallest device length that will keep the channel length...
Hi guys, thanks for the reply. I really appreciate it! Yes, I think I need to use 10uv for signal input instead of 10m and it comes to be OK after I change that. Sorry for not explaining things clearly, for I'm still pretty new to this domain.
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Hi, I was just trying to find the gain of a differential stage using cadence. It's a two stage op amp, with the first stage of single-ended differential and second stage of common source. While I fix the other parameters and configuration and change the signal voltage input of the differential...
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