Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

How to pick worst case INL/DNL for DAC corner analysis?

Status
Not open for further replies.

ray.deng

Newbie level 6
Joined
Dec 14, 2009
Messages
12
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,406
I'm using current steering architecture and after running corner analysis in cadence, I have a bunch of plots cluttered together at the output. I was confused on picking the one that has the worst case INL/DNL. Anybody has any suggestion?
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top