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Recent content by RAVI30

  1. R

    Error:NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives:

    Hi, I design protocol, but when i implementing the design using ZYBO board. i have used constraint file, but i get Error when translating the design, Error is: ERROR:NgdBuild:924 - input pad net 'clk' is driving non-buffer primitives:
  2. R

    MIL-STD-1553 verification

    Hi i am working on the Protocol MIL-STD-1553 verification. I need to know that that case should be verify? What the componets of the testbench should incloued? And how this test case should be generated? Give some basic information of the testbench or verification of the 1553 protocol?
  3. R

    How to increases frequency of the VHDL design

    k thank you - - - Updated - - - i have used Xilinx IP memory core so in placing and routing it giving error....
  4. R

    How to increases frequency of the VHDL design

    Minimum period: 13.685ns (Maximum Frequency: 73.071MHz) Minimum input arrival time before clock: 6.880ns Maximum output required time after clock: 5.248ns Maximum combinational path delay: 1.342ns this my synthesized report.....
  5. R

    How to increases frequency of the VHDL design

    k thank you so much....
  6. R

    How to increases frequency of the VHDL design

    I have synthesized my LDPC block code in xilinx ISE tool after synthesized it is giving 73.0753MHZ freq...
  7. R

    How to increases frequency of the VHDL design

    HI... I m implementing LDPC encoder for DVB-T2 as a my final year project , I have implemented but it giving 73MHz(I have using SPARTEN-3A DSP FPGA) frequency but i need 100MHz frequency, so plz help me to increases the frq
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    BCH decoder Implementation on FPGA

    hi.... i am doing BCH decoder implementation in FPGA. plz send some informations and related documented to Hardware implementation of BCH decoder ...
  9. R

    Integer multiplication

    Thank you so much to every one.....
  10. R

    Integer multiplication

    Sorry i didn't got ur point....
  11. R

    Integer multiplication

    Hi.... i am need to use integer multiplication in my design both are integers only... but while simulating the multiplication result is coming as zero....... my design is as folloes ..................................................................... library IEEE; use IEEE.STD_LOGIC_1164.ALL...
  12. R

    ROM memory use in modelsim simulation

    ya i have added all file in project.... plz can u tell source file extension..
  13. R

    ROM memory use in modelsim simulation

    HI.... I have generated ROM block with help of xilinx 12.1 and i have initialized the ROM/RAM block with some values (tried for both blocks) .... but when i simulating this one with help of MODELSIM but it was not simultating giving as error : Loading work.blk_mem_gen_v4_1(blk_mem_gen_v4_1_a) #...
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    BCH decoder Implementation on FPGA

    Hi..... I am Implementing BCH decoder In FPGA... so in syndrome calculation for BCH decoder .... we need to multiply the input data with ALPHA .... so please any one can send the ALPHA values ....
  15. R

    Array For Large Values

    k... then delay will more.....
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