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how pll locked
Hi, you can use XOR for the Up and Down signals and take the out after certain delay time
if we have lock, the Up and Down signal are the same
Best regards,
Rania
On Spectre you can use the noise analysis and then choose the noise source to be your input and the output is the OpAmp output
Run the simulation
go to Results-->Print-->Noise Summary
Rania
Re: PLL design
Try the PLL Chapter on Razavi as a start then you can read the CMOS PLL Synthesizers: Analysis and Design by Keliu Shu & Edgar Sánchez-Sinencio
Rania
Aslam Aliokm Shohdy,
The smaller mismatch you have, the more perfect charge pump you get. Typical value is 1%
the mismatch is defined as (Iup-Idown)/Iup *100
best regards,
Rania
Added after 6 minutes:
Hi,
The charge pump consists of current sources to generate Iup and Idown
for proper...
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