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Hi rca , thanks for your reply.
but perl also has capability to run processes in parallel.If tool is made in such a way that to support perl means then it is possible i think.I dont know i am just discussing
Why cant we use PERL for asic design verification as it has very good features as compared to System verilog?
Some important features of System verilog :
Features inherited from Verilog HDL,VHDL,C
Constrained-random stimulus generation
Functional coverage
Interfaces...
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