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While at the time of fabrication, DRAM also required cap which is formed using Trench in cmos process. On the other hand in SRAM, all components are transistors only which is easier to fabricate.
Also tell me how 1T DRAM (1mos+1cap) is taking more area as compare to 6T SRAM( 6 mos transistors)...
suppose any Voltage current feedback network is implemented and we have calculated its Aβ (loop gain) then how will i found its input /output impedance from this expression . Figure is given below for a reference
I have calculated Aβ as -gm1 ro1 {Rs gm / (1+ gm Rs)}
Re: which take more time to access address in two different memories of 8byte & 16by
I got the answer of my question in your above statement. Yes i am agree with you there can be many types of memories which will decide the delay.
But for a beginner like me, i consider a very normal case of...
Re: which take more time to access address in two different memories of 8byte n 16by
Its Kilo-byte.
Suppose i have two different memories, one has its size to be 8 Kbyte and another has 16Kbyte.
I want to access one location (specified by address) on each of the the memory. Which will take...
which take more time to access address in two different memories of 8byte & 16byte?
If i want to access particular address in two given different memory sizes i.e. 8 byte and 16 byte. Which will take more time any why? How is these decoders works while accessing any memory?
Analog IC book which have latest design techniques based on latest technology node
Almost everybody start one's journey of Analog IC design with the Razavi book titled as "Design of Analog CMOS IC" which was adopted in early 2002.
After 2006 many people suggest to pick Analog Design essentials...
Thank you! Totally agree with you. Even i got the same answers. except according to me common mode gain is = -Rl*gm/(1 + 2gm*Rs) = Rl/2Rs. instead of (gm*Rl )/2Rs (you have written)
Am i correct here??
Explanation is required. when small signal differential inputs are given to differential amplifier.
Two cases are given in attached figure
(A) When current source is ideal
(B) When current source is practical i.e. have one finite resistance.
If input is given as V1=1sinwt and V2=-1sinwt and...
Re: Difference between Input common mode level & bias voltage for differential amplif
I set that noise condition while taking a default consideration of bias (i.e. Vbias is already applied to keep it into saturation). you can't conclude that Input common mode voltage is always DC value. As in...
In general differential amplifier with resistive load need to add current source at the source of both the transistors to make its bias current Id1+Id2 independent from of common mode input voltage.
In the given figure is it still required to add a current source at the source of both such...
Re: Difference between Input common mode level & bias voltage for differential amplif
thank you for your answer. I am agree with you but common mode voltage can also be sinusoid in given condition. suppose i am adding a noise sinusoidal signal on both the terminals of differential amplifier...
Difference between Input common mode level & bias voltage for differential amplifier
Hi
If i have designed a common mode differential amplifier using nMOS structure (resistance as load). In this case what is the difference between input common mode level and Vbias for this circuit. What is...
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