Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by raguna

  1. R

    [SOLVED] Cadence Virtuoso and MMSIM installation

    Hi all, Installing IC615 into virtuoso folder went fine, but the configuration failed. Can someone please help fixing this issue. Thanks.
  2. R

    high frequency square wave/clock generation from a low freq. clock using PLL

    Hi Funkymix 89, Did you find the component you are looking? Thanks, Rag
  3. R

    60MHz clock generation

    I have simulated a clipping circuit by using a 60MHz 8Vpp sine wave and clipping it using 1N914 diodes at 3.3V, to generate approximately 3.3 VDC square wave. But, when I tried the same with my function generator and PCB, I see that 8Vpp sine is attenuated at that frequency and the does not clip...
  4. R

    MOSCAP of 1nF in AMI 0.5um

    Thanks Domink and nitishn5, I used a multiple units of a smaller device and it works fine. Thanks again.
  5. R

    multiphase Clock generation

    Thanks dick_freebird! I used anit-phase skew correction technique from a paper and fixed the issue. Thanks again!!
  6. R

    Gate driver design with two branches driving two different transistors

    Hi all! I considered an equivalent of two parallel capacitors and does the math. It works fine by doing that. Thanks all!!
  7. R

    DRC Error : Poly2 to unrelated metal1 spacing is 0.6um

    Hi all, I told the fab to ignore that error and everything works fine after it came from fab. Thanks all.
  8. R

    60MHz clock generation

    Hi all! How can I generate a (0 to 3.3V) 60MHz sharp edge clock. I can get upto 100MHz sine wave with my function/signal generator. If I use any high speed comparator, there is always an offset( around 0.2V) at the output. Can I have some option/methods for its generation. Thanks
  9. R

    [SOLVED] Unsigned and Signed Addition and subtraction VHDL

    Hi TrickyDicky! Thanks for your reply. I am having a syntax problem saying,"Can't determine the definition of operator "+"" library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; --use IEEE.STD_LOGIC_SIGNED.ALL; --use IEEE.STD_LOGIC_UNSIGNED.ALL...
  10. R

    [SOLVED] Unsigned and Signed Addition and subtraction VHDL

    Hi all! I am trying to design an ALU which does signed addition & subtraction and unsigned addition & subtraction. I have following code written, but does not work. For unsigned : I used simple R<= A+B and R<= A-B; for addition and subtraction For Signed: I tried to change the type of A,B to...
  11. R

    MOSCAP of 1nF in AMI 0.5um

    Hi all, How to design a MOSCAP of 1nF in in AMI 0.5um process(Cox=2.47fF/um^2). I tried using C=Cox.W.L. But, this was not working fine.
  12. R

    DRC Error : Poly2 to unrelated metal1 spacing is 0.6um

    Hi Erikl,
  13. R

    DRC Error : Poly2 to unrelated metal1 spacing is 0.6um

    Hi, I am designing a capacitor with low parasitics. I tried to layout with (Poly1 conntected to M1) with (Poly2 conntected to M2). After I layout Nwell+Poly1+poly2, there was no DRC, but after I add metal 1 on it, it has a DRC error "Poly2 to unrelated metal1 spacing is 0.6um". I am designing in...
  14. R

    multiphase Clock generation

    Hi Dick_freebird! Thanks for your reply. I used a Johnson counter and ripple counter to generate 5 phase clocks. But, when it comes to the last flip-flop there is a long skew which is collected along the path. Is there any way I could generate with low skew? I am looking for low power...
  15. R

    multiphase Clock generation

    Hi! Thanks for your reply. If there is no limitation of the jitter, how can I generate five 15MHz multiphase clocks?
See more

Part and Inventory Search

Back
Top