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Hi umerarain,
You should try with this code (not in a process) :
External_bus <= a when Output_enable = '1' else (others => 'Z');
If you want to keep your process, add signal a in your sensitive list.
clock gating cell code
Hi gerade,
When you write :
clock_gating_latch : process (CP, latch_enable_s)
begin
if (CP = '0') then
clk_latched_s <= latch_enable_s;
end if;
end process clock_gating_latch;
I understand that you want to latch the value of latch_enable_s on falling edge...
delay in cpld
Hi catrat,
For @ltera device, you can to this by adding LCELL component.
in vhdl, the LCELL declaration is :
COMPONENT LCELL
PORT (a_in : IN STD_LOGIC;
a_out: OUT STD_LOGIC);
END COMPONENT;
The @ltera tool will take the LCELL component in its library.
This will...
Hi smartshashi,
I've looked at your design and have some advice for your mem component :
- do not use inout internal signal, use a data_in bus and a data out bus
- in your process, try to write a code with if ... elsif ... else ... end if, instead of data<= xxxx; if ... then data <= yyyy; end...
Hi osbourne,
You seems to have 3 clock signals as input of your design and may be only two clock route available (buffer + global route)...
Which device do you target ?
Do you really need 3 input clock ?
ram problem codes
Hi,
The LPM_RAM_DQ is only a macrofunction for single port embedeed ram.
If your target is an altera, just declare your component and map it in Verilog.
If your target is an other component, you may code in verilog a similar bloc ram :
Look at this coming from Xilinx...
Re: fuction call within state machine.execution time of func
Hi chaitu2k,
I don't think that you can use a synchronous function (that means it contains clocked process = Flip Flop) to affect a signal in an combinatorial process.
The function may only generate combinatorial.
If your signal...
Hi arshad_mir,
Remember that what you write in vhdl describes logic elements or flip flop.
when you use my_signal'event argument, the sysnthesiser will always map my_signal on the clock input of a flilp flop (or inverted clock for falling edge ...).
What you seems to want to do is to detect a...
Hi,
I suggest you an USB scrolling display. This product should :
- have an USB connection
- display a message on a LED screen with scrolling effect
- be parametrized by a PC
We can imagine that the LED screen is big to be seen in the street for advertising, or that the screen is very small to...
Hi,
I think that the recommendation of providing only component mapping on a top architecture comes from re-use constraints.
If your design is correctly defined, all the functions are integrated in your different components. Your component may be reused "as it is" in an other design.
The only...
Re: vhdl Q?
Hi,
Do not ever forget that you are describing flip flop register and logic gate combinations when you write synthesisable vhdl.
When I write delay_trig <= trig, that means that i want the D input of my flip flop to be connected to the trig signal.
in a RTL view, you will have ...
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