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Recent content by quanble

  1. Q

    voltage reference problem

    Why do you use so short time step ? Try use longer time pwl singal ( uS) .
  2. Q

    Use of decoupling cap either from PMOS or NMOS

    Hi, Rania Why NMOS gives larger capacitance than PMOS for the same aspect ratio in the same process ?Both NMOS and PMOS capacitor are caculated by planer capacitor formula .They have same oxide thickness ,so the value is equal.
  3. Q

    About LDO compensation

    A cap in series resistor can get a zole and the resistor can be generated by a MOS output resistor.
  4. Q

    The size of pmos pass transistor in LDO regulator

    pmos vs nmos ldo pass transistor PMOS size is decided by max output current .You must make the pass MOS gate voltage still keep the input diff pair and pass MOS in saturation region .
  5. Q

    How to size the transistors in an opamp

    Larger L of M1-M4 can increase output resistor and larger M1-M4 W/L increase the output swing.Hower ,at the cost of noise attenuation.
  6. Q

    How to decide PLL LoopBandwidths?

    Could you tell me why the bandwidth should choose less than 1/10 of input frequency in more deepth ?or do you have some doc about this topic?
  7. Q

    What is "Worst Case Simulation"?

    HI,Why the MAX temperature is the worst case when calculate the delay time ? As we kouw ,the VTH reduce when temperature increase.So, in my opinion ,the worst case should been ss process ,min voltage and min temp. Correct me if mistake.
  8. Q

    How to design a pure coms process bandgap?

    if don't have parasitic bjt,you can use pure CMOS to get a cmos voltage reference.But it's not called bandgap. You can find some papers about cmos voltage reference in IEEE.

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