Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
if peak voltage is small not several ten volt
you can prepair odd number inverters and even number inverters
then take AND
if you use CMOS device for 130nm , the pulse width is around
the
single inverter propagation delay that is 50 pSEC without pad capacitor
nor LOAD capacitor
addition to upward guys opinion
you may consider the variation caused from the etching error.
you need the device data showing (1/(sq root W*L))
and you need some effort to find proper L to keep the ratio if Id.
its reliability issue. the fowler nordheim current pull the moving ion in sio2. and trap the ion. it causes current path in sio2. so voltage stressed to sio2 and time are some function of breakdown of gate oxide.
circuits under bond pads
i do not suggest to use active area nor ESD circuit beneath pad. i only know the register was located beneath it on 2 um rule for LCD panel driver. but deep sub-micron process causes huge mechanical stress, even register will have gig fluctuation of characteristics.
analog design automation is not accomplished yet. as far as i know the optimiser was released but performance was poor. nec-not numerical electromagnetic code-has bipolar analog libraly. performance is so so.
sram hspice
usually the leakage current of MOSFET is 1E-15A \depends on Vth swing channel length and width.
so if u want to simulate 6T cell
u have to make the fitting of spice parameter for sub threshold area
if u look UCB formula sub threshold area is different behavior from satulation or...
Re: DRC Rule Question
i think the reason why M2-M5 design rule is looser than M1 is ;
even we use CMP, M2-M6 has some up and down beneath them.
and M2-M5 are used for Vdd Vss considering reliability.
for M1 thickness is smaller than M2-M5 so etching M1 is easyer than M2-M5 it brings to us the...
the meaning of matching is for MOSFET;
mosfet beta is defined the channel L and W and Vth and oters when fabricating MOSFET , there is some difference between MOSFET even they are very closly layouted caused from etching or neigbering device.
so MOSFET matching is the facter of distance between...
layout patterned ground shield
i also think there is no automatic deign tool for ground shield.
important item is to reduce the eddy current loss, for its simulation i use ADS or ASITIC:opensource aplying 3d electromagnetic characteristics to obtain "Q" of inductor \\ADS is nly 2 and half...
Re: Level Shifting in CMOS
the voltage gain of source folloer is less than 0dB because the out put voltage shall be devided by source resistance/( source resistance+1/conductance of MOS)
but u can shink current so means power gain is bigger
for level shifting you can use source folloer but...
Re: pll design
pll low jitter 1 to 3GHz
i donot know the frequency so my thinking is correct or not for you?
1 for cmos ic, use 2 inverters type osilator (in ADS you can find as saple)
i experienced to design colpitts type, unfortunately phase noise was huge because of Vdd and bulk noise...
Re: DRC Rule Question
m1 is lower level metal in the cell, we use m1 as interconnection between transistors so minimum line and space is needed.
m2-m5 are interconnect between cells and do not need so small design rule. m6 is top layer, we use it for VDD VSS and inductor, low resistance is good.
the matching is affected from the thickness of oxide(nitride) , etching speed of x and y axis and circumstances of cell.
i donot know the formula but the most precise etching i.e. design rule times 10 for a side is enough from my test etching result
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
