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hello all,
I am using LPC2292, GCC Compiler.
I am writing code which should handle nested interrupts.
Watchdog is enable and default handler is also written properly (all
interrupts are handled over here).
My problem is:
After 3-4 hours sucessfull transmission and reception of frames,UART...
Please tell how to use the JTAG PORT (only JTAG not EJTAG).
I am trying to use the only the system controller of the IDT but the wiggler (same used for the ARM7)does enter into the debug mode after connection establishment.
What must be the pinouts for the JTAG? Is there any hardware pin to be...
i am not able to install the sde_5.03 lite (binary only version) using the guide(pdf)
can any one explain the steps after reaching to step
$./sdesetup.sh for sde lite
if no fragmentation is done for sim it didnot run the sde-gcc/sde-make etc
in fragmentation step 3 it cannot found the...
dct114
hello all,
how wiggler can be used for the MIPS
(for both jtag and ejtag ports)
MIPS have only onchip cache (program and data) then can u guide me how to use jtag to program the MIPS
Thank you.
Priya
hello pankaj,
have u got the solution for the problem
i am also getting the same problem with xilinux 7.1i version
on test bench waveform i am getting the expected result but after downloading i am getting inverting output for and and nor, not get while for or and nand get it work fine
is...
logic gates not working
hello,
i have develope an test board for the cpld xc95288xl
now when i am using standard gate code
entity ANDTEST is
Port ( A : in std_logic;
B : in std_logic;
Y : out std_logic);
end ANDTEST;
architecture Behavioral of ANDTEST is
SIGNAL...
HELLO,
I WANT AN SHARED MEMORY BETWEEN ARM (LPC2292) AND THE PCI BUS CONTROLLER (PCI 9056-PLX TECHNOLOGY)
LPC2292 HAVE INBUILT EXTERNAL MEMORY CONTROLLER
NOW MY QUESTIONS ARE:
HOW THE SAME SRAM (I.E. SAME ADDRESS AND DATA LINES) CAN BE USED FOR BOTH (LPC2292 AND OCU 9056)?
HOW THE CS...
cpld small board test
hi,
i want to build an test board on my own :-)
can i build it with minimum external devices such as led, switch, etc.
i got some of the schematics for XC9572/36
In those boards 14 Hz johnson counter is connected to GCK1 pin
Can any one explain why it is so?
Priya
hello,
I am working on PCI BUS Project.
I have to connect an cpld to PCI controller chip
I have jtag cable and cpld XC95288XL-10TQ144C with me
Now to program and test the cpld I have to build TEST BOARD (PCB)
no standard xilinux board is available
can you please help me out in this...
hello,
i want to develop an serial card which will be interfaced to pci bus
so.. i will get some data on the pci bus from the serial port
now how i can check whether the data reached properly at the other end of the pci bus
should i develop 2 pci cards to check the communication(which is...
hello friends,
can someone help me to take me out of confusion
i want to build an application going to interface to pci bus (there is no os)
i am refering the book "pci system architecture" by tom shanley
in book chapter 19: configuration register (pg 384) gives how to use base address...
cpld chip
hi,
i want to learn cpld chip programming
which chip i should go for?
does following chips are ok
XC9536xl-10PC44C(3.3)
or XC9536-15PC44C(5V)
priya
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