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Recent content by prcken

  1. prcken

    how to determine sample time and number of samples in TDR matlab code

    Hi any idea about how to define the Ts and # of samples in the code example provided by Matlab? it says measured at 1496 frequencies ranging from 50 MHz to 15 GHz. Ts = 5e-12; N = 5000; % number of samples Thanks KK
  2. prcken

    CPW HFSS Wave Port vs Lumped Port

    Hi I am currently using HFSS simulating a grounded CPW T-line on silicon substrate. I tried with both Wave port and lumped port. But I got very different results. I read that a lot saying that it needs to meet the minimum sizing for wave port depending on the width and spacing of the CPW...
  3. prcken

    how to set lumped Port reference for pad bump simulation in HFSS

    Hi Can anybody help to explain how to assign excitation for this two pads, basically i want to simulate the flip-chip bump. I have assigned ground plane at the top and bottom faces of the dielectric materials. but they are not touching the bottom face of the bottom pad and the top face of the...
  4. prcken

    how many segments of the RLGC model is accurate?

    So I can just estimate the effective wavelength from the transmission signal, e.g. 10Gb/s data rate, just estimate as 10GHz, i don't know what's the microwave index on-chip, so just use speed of the light, then the wavelength of the signal is 3 cm. 1/10 wavelength is 3mm, if my on-chip...
  5. prcken

    how many segments of the RLGC model is accurate?

    Hi if i know the RLGC parameters in terms of Ω/m, H/m, F/m. How many segments (or basically what's the length of each segment) should I set for accurate transmission line model simulation? Any comments about that? Thanks,
  6. prcken

    PLL top-level simulation LC VCO is not oscillating

    after changing the VCO layout, top-level PLL post simulation works from the netlist it show R reduced, i think the R kills the Q so that VCO is dead mr_ni "vcob" 201.219 4.22513e-14 5.86118e-14 mr_ni "vco" 205.062 3.6997e-14 5.42499e-14
  7. prcken

    PLL top-level simulation LC VCO is not oscillating

    Yes, I am using Calibre PEX for extraction. I think that's mean the VCO outputs' parasitic resistance seen respect to the ground. no, it should be just series resistance. if it's to the ground, things will be wrong. I am thinking to modify layout and see and the size extracted calibre file...
  8. prcken

    PLL top-level simulation LC VCO is not oscillating

    yep, 10fF is not much, but i added up to 50fF for standalone VCO post layout simulation, also oscillates. so far I just run both at nominal corner. I want to make sure it works at least at tt corner first, then think about other scenario. is there a possibility that VCO will start to...
  9. prcken

    PLL top-level simulation LC VCO is not oscillating

    yes, i did consider divider and VCO buffer load, VCO alone works fine with post-layout simulation. I have add another 10fF parasitic cap. no MC, sensitivity simulation yet.
  10. prcken

    PLL top-level simulation LC VCO is not oscillating

    Hi, I have a PLL target running at 12.5GHz. Schematic top level works. Standalone post-layout VCO also works. But top level post-layout PLL simulation is not working. I've tried all the methods i can think of: 1. add initial condition at VCO outputs; 2. set max. step. 3. add a current pulse...
  11. prcken

    long length signal wire on-chip risky?

    I don't know how to extract as distributed RLGC, i think Calibre only extracts as a lumped RLC. I will try to do extract simulation and see the eye diagram.
  12. prcken

    long length signal wire on-chip risky?

    Hi I am doing layout for a >10Gbps signal. but due to practical issue the signal wire is very long in the layout (>1mm as the red arrow indicates in the uploaded picture) Is that risky? I think it has to be treated as a transmission line now? But it seems impossible to add extra termination...
  13. prcken

    dc offset cancellation

    In the case you said the opamp is like a high speed comparator. I think the opamp will go crazy or retarded without the LP filter at the opamp input, the signal swing came out of the the LA is not that small and also at very high-speed.
  14. prcken

    dc offset cancellation

    HI erikl, I didn't implement OT (and DAC trimming) so far. I replaced the opamp to a VCVS with a gain of 1000(like an ideal opamp). found that it takes long time (>10us) for the feedback voltage to track at the middle level of the TIA output. so I think it will finally move to the middle...
  15. prcken

    dc offset cancellation

    Hi, I am simulating this RX. Had a problem with the feedback loop. I am wondering why the feedback voltage (output of the opamp) cannot be centered about the output voltage of the TIA, so that the final differential eyediagram cannot be centered around 0V, it has offset. I checked the loop...
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