Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi,
I'm synthesizing a digital core using Synopsys DC, with a given clock, and I will later use this clock to drive the next blocks. Since the network will introduce a clock latency, I wanted a dedicated clock out port which outputs this delayed clock.
How do I go about it?
I tried to just to...
Hi,
I'm designing a Delta Sigma modulator, and synthesizing it using SOC encounter. When I design the clock tree and choose the buffers and inverters to be used, Encounter always choose the largest buffer as the first stage, which shouldn't be. the later stages are smaller!. Is there a place...
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
