praveenkrs
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Hi,
I'm designing a Delta Sigma modulator, and synthesizing it using SOC encounter. When I design the clock tree and choose the buffers and inverters to be used, Encounter always choose the largest buffer as the first stage, which shouldn't be. the later stages are smaller!. Is there a place where I need to set the driveability of the external clockdriver?
I did put a line set_driving_celll -lib_cell INVD4LVT [get_ports clk] in the sdc file, but that doesn't need to help.
So I wanted to know if there was a way to correctly size the first stage of the clock tree.
I'm designing a Delta Sigma modulator, and synthesizing it using SOC encounter. When I design the clock tree and choose the buffers and inverters to be used, Encounter always choose the largest buffer as the first stage, which shouldn't be. the later stages are smaller!. Is there a place where I need to set the driveability of the external clockdriver?
I did put a line set_driving_celll -lib_cell INVD4LVT [get_ports clk] in the sdc file, but that doesn't need to help.
So I wanted to know if there was a way to correctly size the first stage of the clock tree.
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