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Recent content by praveen24

  1. P

    Diffrent colors to shapes

    Read the query first and give your answers. Don't mislead. Actually @maormat4 asked about the place bound top. I think it related to the component rather than nets.
  2. P

    Diffrent colors to shapes

    Hi, You may assign color to components in 2D mode itself as you desired. While changing that to 3D, you will get. For better view in 3D use altium.
  3. P

    Cadence Allegro: Same Net Spacing DRCerrors(Clearence)

    Hi, I think tool couldn't support that. I drew a track 7.5 mils away from GND shape region and connected other end to GND shape directly. (Same net spacing between track to shape is 10 mils) Now it's showing the drc error near the region of 7.5 mil like the same net spacing is less than 10 mil...
  4. P

    Routing error with ares

    Hi, Check the properties of red colored track connection between the vias. It may be in non-electrical one.
  5. P

    IPC CID program- Clarification regarding exams

    Hi all, I want to clear IPC CID exam . Now I am searching for the previous year questions related to that. If you know anything( ideas,links,and etc,.. ) Kindly share for me. Thanks all.
  6. P

    footprint in Allegro

    Before going to run .bat file do the following Just open the empty .dra file and set the psm and pad path. Move the unzipped file to the location which u mentioned for paths. Run the .bat file. It will work.
  7. P

    footprint in Allegro

    Unzip the downloaded file. Run the .bat file in that. Before that set psm and pad path in your .dra file in advance.
  8. P

    keep-out area around footprint

    For footprint of each component have any layer???????????
  9. P

    keep-out area around footprint

    It can't change directly on board. For that you modify in footprint at first. Then update in board . In (allegro PCB editor)place option drop-down has manually option in that select package symbol. From that update it.
  10. P

    keep-out area around footprint

    From my understanding you speak about the place bound top of footprint. Due to that you suffer while placing the component. Edit (reduce) that place bound area as you want. And try that.
  11. P

    keep-out area around footprint

    what type of keepout u desired to mean? (whether package or route)
  12. P

    pcb allegro in cadence

    To know the possibility (whether present or not) only i ask that. now i am clear.
  13. P

    Difference between FINFET and conventional MOSFET

    FinFETs possess the following key advantages over bulk MOSFETs: reduced leakage,excellent subthreshold slope, and better voltage gain without degradation of noise or linearity. This makes them attractive for digital and low-frequency RF applications around 5 GHz, wherethe performance-power...
  14. P

    pcb allegro in cadence

    hi, thanks for your response. My customer needs four board as a stack-up and specific component structure for each.In that first and fourth board does not have more component 2 layer is enough for that routing of that. But second one has FPGA. So it requires minimum 4 layers. If any possibility...
  15. P

    pcb allegro in cadence

    hi, i have the board file which consist of 4 board in one. but i have problem with while creating layer for a board in different level for example first one-2 layer,second one-6 layer like wise. any possibility in that . please help me.

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