Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by PRAVEEN HV

  1. P

    Closing a form after ipc process ended in cadence SKILL

    Hi all, I ran some process and invoked one form. Now I want to close the form after tat process exited. I am trying with IsActiveProcess(pid). But its not working. When I tried directly in CIW its working. But through skill its not working. Please give me a solution. Thanks & regards, Praveen
  2. P

    IR drop with respect to layout

    How power interleaving method will reduce IR drop??
  3. P

    IR drop with respect to layout

    Hi, Can anybody give the detailed information about IR drop and how to avoid it??? thank u in advance
  4. P

    Skill code to convert Polygon to Rectangle

    Hi Can anybody tel me how to divide polygon into rectangle in Skill without using dbLayerTile() function.
  5. P

    Move objects using SKILL

    HI, I am a beginer to SKILL.. Please tell me 1)how to use bindkeys to increase or decrease row/column of Vias 2)The script should take a bbox as input and should put contact/vias in specified box given the top and bottom metal. Thank you, Praveen HV
  6. P

    divider synthesize error

    It is not showing the line of error.. Insted i'm getting as below.. plz help me.. ERROR:Xst:2587 - Port <new_r> of instance <g1[0].cell> has different type in definition <nr_r4_half_cell>. ERROR:Xst:2587 - Port <op_3y> of instance <g1[0].cell> has different type in definition...
  7. P

    divider synthesize error

    hi sir i'm getting following errors.. ERROR:Xst:2587 - Port <new_r> of instance <g1[0].cell> has different type in definition <nr_r4_half_cell>. ERROR:Xst:2587 - Port <op_3y> of instance <g1[0].cell> has different type in definition <nr_r4_half_cell>. ERROR:Xst:2587 - Port <op_r> of instance...
  8. P

    divider synthesize error

    Hi, I've attached division code, simulation result is correct but while synthesizing i'm getting following error.. plz anybody fix this error...???? thank u.. "ERROR:Xst:2587 Port <port_name> of instance <inst_name> has different type in definition <def_name>"
  9. P

    How to include clock???

    Thank u , I have code for components and attatched to my project file and included in main code.. but those are without clock.. I'll try to add clock to those and ll try..
  10. P

    How to include clock???

    structural means I'm using components and then mapping those using port map.. Can I use port map inside the process statement????
  11. P

    How to include clock???

    Hi, I am implementing some equations in VHDL.. and I need 'n' iterations.. after each iteration i need to update the input with the results from first iteration.. and also I've to get result of first iteration in first period of clock, second iteration output in second period of clock and so...
  12. P

    VHDL code for a square root of a real number????

    sir i use double precision format.. Is square root operator for floating point number is available in new versions of XILINX??? If so can it be synthesisable in sparten-3????
  13. P

    VHDL code for a square root of a real number????

    Hi siskin, Thanks for ur help, i need square root for floating pont number and also range is not specified so i have to calculate for different values.. is any CORDIC algorithm for square root of a floating pont number????
  14. P

    VHDL code for a square root of a real number????

    Hi can any body tell how a square root of a real number can be calculated using VHDL????
  15. P

    How to burn HDL code on Spartan 3e FPGA?

    Can any body tell me the procedure to burn the hdl code on fpga sparten-3e kit...???? Plzzz help me...
See more

Part and Inventory Search

Back
Top