How to include clock???

[PRAVEEN HV]

Hi,
I am implementing some equations in VHDL.. and I need 'n' iterations.. after each iteration i need to update the input with the results from first iteration.. and also I've to get result of first iteration in first period of clock, second iteration output in second period of clock and so on..

but I'm not getting how to include clock... bcz I've used structural flow so I cant include process.. please help me in solving this problem...

 

[matrix83]

send me ur code........then i can help u out

 

[TrickyDicky]

What is the "structural flow"? did you define the entities? if you did, then you can include a clock in them and write processes.

 

[PRAVEEN HV]

structural means I'm using components and then mapping those using port map.. Can I use port map inside the process statement????

 

[TrickyDicky]

no you cannot, but where are you getting the components from? did you write them? if you wrote them, then you can simply add a clock, as at the bottom, there will be processes, or if you are mad and did the whole thing with primitives, you need to chose the clocked primitives. if someone else wrote them, then get the clocked versions.

 

[PRAVEEN HV]

Thank u , I have code for components and attatched to my project file and included in main code.. but those are without clock.. I'll try to add clock to those and ll try..

 

[vineetkumar1992]

how can i use component instantiation block and generate statement under process statement??

 

[K-J]

how can i use component instantiation block and generate statement under process statement??

As mentioned in your other post, the answer is...You can't. A process can call functions or procedures, that's it.

Kevin Jennings