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Recent content by polu

  1. P

    System Verilog restriction on assignments/NBA

    Hi, System verilog LRM says: Automatic variables and members or elements of dynamic variables—class properties and dynamically sized variables—shall not be written with nonblocking, continuous, or procedural continuous assignments. References to automatic variables and elements or members of...
  2. P

    Reg excempting timing arc check

    Hi chaitubek, Thanks for your reply. But the clocks are not having any MCP relation...say clk1 is period is 1.4ns and clk2 period is 1.5ns. Common multiples between these particular clocks comes out to be 0.1ns, 0.2ns, 0.3ns ...etc. Here LCM is 0.1ns....I want the check to be...
  3. P

    Reg excempting timing arc check

    Hi, I am having data flowing from a flop running at a higher frequency to a flop running at lower frequency. Its not a MCP. Let us say the time periods are Tx and Ty ( Tx < Ty) I have an enable signal to allow the data transfer between theese flops. Say for every 'n' clocks once the data...
  4. P

    setting post layout clock transition using PT

    All, I am basically looking for what difference the following settings can bring in the clock transition in a post layout netlist. 1) set_propogated_clock 2) set_clock_transition_delay set_propogated_clock Ofcourse, prelayout setting happens to be just set_clock_transition...
  5. P

    Help me fix my code for checking one bit in one clock (Verilog)

    Re: verilog error check Your code is written to check all hte bits on a clock edge. You could write the code something like below.... i =31; always@(posedge clk) begin if(i >= 0 && i<=31 && addr[i] == 0) i = i - 1; else j = i; end 'J' holds the address value which...
  6. P

    The difference between structure and union in System Verilog

    HI, Can somebody explain the difference between structure and union in system verilog and the reason for the existence of the both. Thanx.
  7. P

    Please explain to me Tcq,cd+Tlogic> Thold

    Re: Reg T_hold All, I have read in some textbook that Tcq,cd+Tlogic > Thold. Can somebody explain this condition. Rgds, Kiran Polu Added after 1 minutes: In this discussion there are two flip flops with a combo logic between them. Here Tcq,cd is the clock to Q delay in the flip flop and...
  8. P

    What's the role of Perl in VLSI?

    Re: perl Any more linx on perl for VLSI. Like the one above http://www.kwcpa.com/tools/ is good.
  9. P

    pipelining in verilog

    You can have independent block of code for, say 5 stages of ur processor pipeline......When U give a common clock for all these units and when output of one unit is connected to the following unit...that automatically creates a pipeline..since each unit processing the data from the previous unit...
  10. P

    System C & system Verilog

    As per my knowledge systemC is a language with only models..it will not appeal anything that can be realized as a hardware...Where as System verilog is for both hardware realization and it's functional verification.
  11. P

    E as the verification language in comparison with others

    Re: E is the only one? E is one of the most popular verification languages even today....
  12. P

    VERIFICATION METHODOLOGY

    Does anybody knew any link that educates on different verification methodologies and comparision by taking a core generic architecture as DUT.
  13. P

    Need a tutorial for entire digital design flow

    Does anybody have the tutorial of entire digital design flow.If so please send me the link or the tutorial.I am looking for some good file:). Thanx in advance.
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