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calibre lvs recognize pins
Actually, LVS is working now! I guess depending on the PDK (I am using IBM 65nm cmos10lpe), the layer needed might be different. Turned out that I have to Create -> Label with the "lbl" (label) layer with the matching metal/poly.
I also disabled the environment...
calibre lvs diode between vdd gnd
hello, thanks both for your replies.
I am using Cadence Virtuoso IC 6.1.3 layout editor. I am fairly sure that I selected the right material in the LSW before I place pins/labels. For example, my VDD and ground rails are on metal 1, so I select "M1: drw"...
calibre lvs
Hello all,
I am having trouble with Calibre LVS. My problem is that Calibre LVS does not recognize the pins I placed in the layout. For example, in an inverter my schematic has 4 ports (in, out, vdd!, gnd!) but Calibre LVS states that my layout has 0 port, despite I labeled all 4...
assura qrc
Hello, I am having trouble running Assura RCX. I am currently using Cadence Virtuoso 6.1.3 with IBM PDK cmos10lpe (65nm). I ran Assura LVS on a simple inverter cell and it has no probem passing LVS check (I ran DRC on the same inverter with Synopsys Hercules because the IBM PDK that...
ibm what is drc index
Hello,
I have a general question about DRC.
I was using Synopsys Hercules to run DRC on a simple inverter circuit built with 65nm IBM PDK (cmos10lpe) and I got some errors. Then I decided to erase everything and instantiate a single cell (nfet) and run DRC on it. To my...
Synopsys Hercules
Hi all,
I was trying to run Synopsys Hercule DRC using Hercule VUE (graphical interface) but I encountered a strange error. Here is the complete error log. The error is near the end of the log.
I am not sure what does the error mean. It looks like it might have something to...
cadence pvs
Hi all,
I have several questions regarding ARM libraries, IBM PDK, and Cadence PVS.
ARM Libraries
1. Has anyone used it before? Does it have layout view for Cadence Virtuoso tool
IBK PDK
1. After I installed it, I got the following warning message in Virtuoso CIW
This is just...
calibre interactive
Calibre Interactive
Hello,
I am looking for a layout verification tool (DRC, LVS, extraction...) and I came across Calibre Interactive. Have anyone used it before?
Does it have everything that I need (DRC, LVS, parasitic extraction)?
Is it easy to install?
How easy is it...
Re: LVS Problem
Thank you for your input. I finally solved the problem today. What happened was the artcpp file sits in <install_dir>/bin/dfII/ but the system administrator at my school didn't set the $PATH variable to that directory. After I did that the problem is gone!
LVS Problem
Hello,
I encountered a LVS problem a week ago. I searched this forum before I post but I think my LVS problem is unique. Here is a section of the error log
When I clicked on the "RUN" button for DivaLVS, the CIW windows said LVS started, but then a pop-up message said the LVS has...
what is pdk or gpdk
Hello,
I have a question regarding the differences between a PDK/CDK (Process/Cadence Design Kit) and a standard cell library. Sometime people use them interchangeably, but I think there are some inherent differences between these two things. Can anyone clarify this?
The...
cmos9flp.
Sorry perhaps I was not clear enough. I think in both NCSU anre GPDK library, there is a file called cds.lib or something like that. So to add these libraries I can simply go to CIW -> Tools -> Library Path, and add library there by loading cds.lib. However for the IBM CMS9FLP I do...
Hello all,
I was wondering if there is a tool/methodology that converts Magic layout to Cadence layout. What happened is my group has a chip layout design in Magic and we want to fabricate it. Since the layout is quite large, we are trying to see if there is a simple way to convert Magic layout...
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