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Dear all:
In a pipelined ADC,
If the input range is -Vref~+Vref
1.5bit/stage
So every stage need two comparators, with the threshold of -(1/4)Vref and +(1/4)Vref.
My question is : what is the tolerated range of the offset of the comparators?
Thanks.
I designed an ADC , in simultion, it acquired 1Gsamples with the 8 bit resolution, after fabricated in 0.18um process, the experimental result is much worse.
Can anyone tell me the reason?
Or what restrict the performance of an analog circuit after the fabrication?
Thans a lot.
Dear all,
During simulation using hspice,how can we get the value of the input capacitance of an opamp?
or to be simple, how can we get the value of the capacitance (Cgs or Cgd) of a MOS?
Thanks.
yxo, thank you for your reply.
I know we use the tested SNDR in the definition of the ENOB of the AD. That's why I presented this question.
Added after 5 minutes:
《A bipolar 2-GSample s track-and-hold amplifier(THA) in 0.35um SiGe technology》
this paper presented the exact formula I...
Some papers(all of them used the bipolar process) said that the ENOB of a SHA is obtained by this formula:
ENOB=(|THD|-1.76)/6.02
is that right?
Or can we use this fomula in CMOS process?
Why don't use SNDR instead?
Where can I find the original explanation?
Thanks you.
pikky
In a paper i read:
“to complish the resolution we designed, the least f3dB should large enough:
f3dB>=fin*[2e((N-1)/2)]
fin is the frequency of the input signal;N is the resolution of the sample switch.
“in the short-channel model, the Ron of the switch :...
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