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integrator output
Dear all:
I am now desinging a 2nd-order sigma delta modulator.
The architecture is gain=0.5 in both Integrator. ( Boser / Wooley 1988)
I use simulink to run simulation. (SDT Tool
by S. Brigati Ver.(0.1) 08/04/98)
Input: 0.5 sinewave
Quantizer: +1...
Hi, all:
According to the SAR ADC circuit below, I can't figure out how this ADC works by adding CS & CATT.
Can anyone give me some hints?
Thanks a lot!
hspice save load
I use .save and .load to speed up the simulation .
in first step , I save the operating point for initial condition
.tran 1u 62.09m
.save type=.nodeset file=top.ic time=62.09m
in secend step, I use .load command
.tran .1n 62.1m
.load file=top.ic
but Hspice seems to...
phase delay simulink
Dear all:
I want to do the image rejection receiver using Simulink.
But I can not do the "90 degree phase shift" in Simulink.
Any one have good suggestions?
Thanks!
I want to design a differential to single-ended amplifier.
Input: 0~vdd full swing 500MHz sine wave (vdd=2.7v, 0.5um cmos tech)
The circuit is as following.
My question is the output is not at 50% duty cycle
Can anyone give me some advise.
Dear all :
I have a question about Hspice.
How to plot the graph of the effective capacitance between 2 nodes.
Between these two nodes, there are some elements.
For example, "G" and "B" in the following circuit
Thanks a lot!
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