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Hi,
Our testing engineer told me he can not convert the WGL due to the MUXClock mode in my at-speed ATPG patterns.
I checked UserGuide and it seems by creating "_fast_WFT_" waveform format and then using it in capture_CLK procedure can fix it. But I always get syntax errors, such as...
I used DFTAdvisor. The command is like:
1. add primary input /.../../scan_mode
which pulls out your internal signal and treats it as primary input
2. setup scan insertion -ten /.../../scan_mode -active high
which defines that signal to be your scan_mode
I believe DFT Compiler has the similar...
Re: help on ATPG ATE test!
Thanks a lot to all!
1. I have only one clk domain, cause all the internal generated clks have been muxed by scan_mode signal;
2. I did stuck-at fault ATPG;
3. Before delivered the patterns, I have ran all the parallel patterns and three serial patterns. All passed...
help on ATPG ATE test!
Hi, everyone,
I generated ATPG patterns using Mentor's Fastscan and simulated with sdf back-annotation. But the test engineer could not get the patterns passed on ATE. And the first fail happens to the 36th pattern (serial) which means the first 35 patterns are fine...
leakage test
How to deal with pure input/output/bi-direction pins in the leakage test?
The reason to keep in reset is to avoid dynamic power consumption?
Any hint will be highly appreciated!
gray code fifo
I see. So the only reason to use grey code is to save the times of flipping. But we do need grey2bin and bin2grey both in real FIFO design, right?
Re: pulse generator
It is an interview question. Assume the width of input pulse (let's say only one pulse) is between 4Tclk and 5Tclk (Tclk is the input clk cycle time) and it could start from any point (may align with the clk edge or not). But the output pulse width needs to be exact twice of...
pulse generator spanish
Could anyone tell me the simplest way to design a pulse generator which will double the width of the input pulse by clocking it? The input pulse width has nothing to do with the clock pulse. Thanks a lot.
Thanks, anssprasad,
What confusing me is that there is no wire or net share the same name in the raw netlist. And for a bus, like pad_dat with 10 bits, only some of them have been renamed, some remain untouched.
So far I did not find any command to constrain renaming.
Any other suggestion?
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