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Recent content by owenljn

  1. O

    [SOLVED] Need help with the finite state machine

    Thank you so much!! I finally fixed the code through another approach, so basically it's a design problem, now this new code is simple and works like a charm: module part2(SW, KEY, LEDG, LEDR); input [1:0] KEY, SW; output [1:0] LEDG; output [17:0] LEDR; reg z; reg [3:0] shifter; reg...
  2. O

    [SOLVED] Need help with the finite state machine

    thanks for reply, so you're suggesting me to use a simulator like Qsim or ModelSim to test it? But the thing is now I've already tested it on board, and it's not working like what I expected, do I still need a simulator?
  3. O

    [SOLVED] Need help with the finite state machine

    I have a DE2 board to test it, I use KEy[0] to jump through states, but I cannot jump from state H to state I, it just stops at state H - - - Updated - - - I kept changing codes to fix the bug where I'm not able to jump from state H to state I with no avail I have a DE2 board as a test...
  4. O

    [SOLVED] Need help with the finite state machine

    I've been spending a whole day to fix the bug inside my code, I'm not asking people to do my homework(since the homework is 99% done but with a bug), I just need help to fix the bug, a simple explanation why the bug exists is appreciated
  5. O

    [SOLVED] Need help with the finite state machine

    Here's the question: We wish to implement a nite state machine (FSM) that recognizes two speci c sequences of applied input symbols, namely four consecutive 1s or four consecutive 0s. There is an input w and an output z. Whenever w = 1 or w = 0 for four consecutive clock pulses the value of z...
  6. O

    Need help with my 4-bit Fibonacci LFSR!!

    ok, here's my working code: module LFSR4bit (KEY, LEDG, HEX0); input [1:0] KEY; output [3:0] LEDG; output [0:6] HEX0; reg [0:3] Q = 4'b0001; always @ ( posedge KEY[0] ) Q <= {Q[3]^Q[2], Q[0:2]}; assign LEDG = Q; QtoHEX Q0 (Q, HEX0); endmodule module QtoHEX (Q, HEX)...
  7. O

    Need help with my 4-bit Fibonacci LFSR!!

    I just fixed it by swaping the concatenation parts So always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[2:0], fib_lfsr[3] ^ fib_lfsr[2]}; Should be always @ ( posedge clk ) fib_lfsr <= {fib_lfsr[3] ^ fib_lfsr[2], fib_lfsr[0:2]}; Now it's working perfectly
  8. O

    Need help with my 4-bit Fibonacci LFSR!!

    I changed to CLOCK_50 which has 50MHz, but now it doesn't even display the "1" every HEX units are displaying "8" just like it's not working and all the four green lights are on but not flashing
  9. O

    Need help with my 4-bit Fibonacci LFSR!!

    it's a key on DE2 board, when I press it down and release, it bounces up
  10. O

    Need help with my 4-bit Fibonacci LFSR!!

    It's a clock key , here's the "clocks" section under timing analysis Clock name Type Period Frequency Rise Fall KEY0 Base 1.000 1000.0 MHz 0.000 0.500
  11. O

    Need help with my 4-bit Fibonacci LFSR!!

    I don't get that annoying warning anymore but the output signal is static, I can't seem to change it by giving it clock signal
  12. O

    Need help with my 4-bit Fibonacci LFSR!!

    Thanks for suggestions, I'm using a book called "Logic and Computer Design Fundamentals" written by M.Morris Mano and Charles R. Kime, and yeah I'm sort of hobbyist, all those simple small gates were from this book - - - Updated - - - wait, it still doesn't work, when you give a seed like...
  13. O

    Need help with my 4-bit Fibonacci LFSR!!

    Thanks for your reply, I'll check this right now, btw I'm not engineering student and I'm totally new to verilog, just started to learn it like two weeks ago
  14. O

    Need help with my 4-bit Fibonacci LFSR!!

    First thanks for clicking in my thread I implemented my design for a 4-bit Fibonacci LFSR, but when I try to compile it, it says warning:No clocks defined in design, it compiles successfully but when I test it on DE2 board, it doesn't work, so here's my verilog code: module LFSR4bit (KEY...
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