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Recent content by oasis

  1. O

    how to import fpga library into debussy

    debussy fpga I'm using debussy to debug my design. But i don't know how to import the fpga library into the environment. anyone could help me?
  2. O

    tools to download for asic design

    usually not. some eda companies provide evaluate version of their tools. but these tools are not so professional i think.
  3. O

    Licensing the use of AMBA SOC bus

    AMBA SOC bus.. amba is an industry standard. it is open. but the arm instruction set is not free. if you want to use the instruction set, you have to buy the license and it is much expensive. in fact, it is almost impossible to afford the license fee. generally, most companies license the arm...
  4. O

    setup, hold, recovery, removal time

    setup hold recovery Hi, i'm confused with these four timing parameters. i know that when the rule of the four parameters is broken, the circuit may enter the metastable status. but how the metastabilities are induced? who could provide any materials about the basic theory?
  5. O

    Licensing the use of AMBA SOC bus

    AMBA SOC bus.. It is an open standard. The spec could be downloaded from AMBA website.
  6. O

    how to break POWER ON password of a note book..

    how to break power-on password turn to the notebook support. if you have the invoice or something else could certify the notebook is yours, the support center would help you to manage it.
  7. O

    why need to avoid using any latches in my design?

    latch loop sta if the design is not aware of the power, flip-flop is prefered. and almost all the latchs could be replaced by flip-flops without changing the function.
  8. O

    Does thhe Apex 20k200ef484-2 have a PLL?

    apex 20ke pll if the part number has "x", for example, -2x, the device has pll; otherwise, it has not. so, apex 20k200ef484-2 has no pll. if you want to use pll, you should choose apex 20k200ef484-2x.
  9. O

    Using 802.11a MAC in a FPGA?

    802.11a MAC the partition of software and hardware is various according to different designs. if the software's process speed is fast enough, some functions, such as WEP, could be implemented in software. but the functions that need quick responds to the incoming data should be implemented in...
  10. O

    How to use pli.a and vcspli.tab to produce a fsdb file in PC environment?

    pli for debussy add the debussy pli option into the vcs command line as a parameter. pls refer to the vcs manual. and add the fsdbdump system task in your testbench to dump the waveform.
  11. O

    Synopsys & Cadence tutorial

    language is just a method, and the key is the circuit itself, such as the system architecture, the algorithm. the description language is changing from low level to high level, but the circuit will not change.
  12. O

    Looking for USB2.0 PHY IP

    as i know, usb phy is designed in the pad. and you could get some information from the ip providers, such as globleunichip in Taiwan.
  13. O

    how to deal with the problem of multiple clock domain?

    the snug paper about the description and synthesis of asynchronous circuits.
  14. O

    waveform editing tool??.

    synapticad timing designer
  15. O

    How to use VCS to analyse the function coverage of a design?

    toggle coverage is used at gate level, and will consume lots of computing materials when doing this coverage analysis. The the others three coverage types could be used at behaviour level.
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