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In Perrott paper, "One can accommodate different quantization step size through appropriate specification of the NTF of ΣΔ". Usually, the step size is assumed to be one VCO period. Anyone can explain it why? or how to determine the step size?
PFD linearity
one factor is called "residual gain enhancement" will affect PFD linearity. Any one can expain what is "residual gain enhancement"? Thanks
pll spur
I want to simulate pll spur by using verilog-A file. simulation tool is spetre. it costs a lot of time. Firstly, I do the transient simu, then to do the fft. Is there any good way to do it? appreciate.
Usually, in the ZIF or LIF design, I & Q mixer use different transconduct stage. However, in recent several papers, I & Q mixer share the same transconduct stage. Apparently, it will increase gm for each mixer branch and result in low NF or high conversion gain. Anyone knows any bad side of...
Saf,
I used self-biased cmos to bias gate voltage. The self-biased cmos also configured as resistor degenarate to overcome the mismatch of bias voltage. If the body connected to the gnd directly, so did the self-biased transistor. So I guess urs is not fit to my case. thanks anyway.
For the below two topology, I thought the linearity of (b) should be better than (a) for there is no body effect. However, the Specture simulation results show that (a) is better than (b). Anyone know why? Thanks
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