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Thank you for your help!:smile:
And do you mean this is not a situation that can be solved by using a jump up mental? Because this method only works in a small number of circumstances? (That's my understanding of the word esoteric~)
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Oh sorry, I just found I made a mistake...
Hi everyone!
In my PLL design, the control voltage of the VCO works on the gate of a PMOS in the amplitude control circuit of the VCO.
In the layout design, the routing of the control voltage is very long,over 1080um, we use M6. And it has been pulled to a PAD so we can test it.
I think we must...
If you want only to do AC analysis, you just have to give the vdd, vss voltages by "vdc source", and add a load capacitance to the output, the voltages of vin+ and vin- can also be given by "vdc source", you only have to give ac values in the right place bisides the dc values.
Now I face a problem when using the Vncap to consist of a 6*6 cap array.
I already find that the cap should be placed on the RX and BP layer when setting the 3rd terminal of VNcap in the schematic to be substrate. And if I just test a single vncap in the LVS ,it can pass; however when I use a...
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