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thanks for your reply. indeed, as a smaller input signal will eventually lead to class B as the transistor won't be switching anymore.
What i don't understand is that when i increase my input signal to the point that my transistor heavily saturates and my efficiency turns very high, my current...
Hello,
i'm currently designing a 3rd harmonic class F amplifier at a few thens of MHz. In simulation I achieve 90% PAE with a reliable model for my active device, but i some things are unclear to me. I understand the principles for class F.
My active device is a BF199. First of all, it seems...
Hello
i use layout xl to draw the designs of my schematics. During layout, sometimes i make small changes to my schematic or i add some decoupling or so. Imagine i take a transistor. During layout i add it in my schematic with S and D to VDD! and bulk and gate to GND!. I "update source", and I...
Hello,
i'm currently designing a 1.25GHz (digital signal) LVDS-like driver to drive an FPGA. Could someone please help me or advise me on the following choices:
- could i avoid internal termination of the transmission line, and hence reduce power consumption for a given swing by half? Assuming...
Re: Help about the code
It seems to me doing lots of operations between 2 cycles is not really a problem. As long as your device has sufficient resources and you ask for a reasonable period. Depending on which toolset you use, as far as i can remember as it has been a while, synthesis can or...
Re: Help about the code
Hello,
if you want synthesisable code, IMO it's better to use std_logic_vectors than integers. If you don't, you should specify a range for your integers. You can hope the tools do this for you, an expensive toolset might, a cheaper one might not do it and just assume a...
A Comparison of CML and LVDS for High - speed Serial Links - AN1202 - Cypress Semiconductor
might help ...
no idea if anyone is still looking at this old post
Hello,
i'm trying to design a ringoscillator working around 10GHz. I'm quite (very) unexperienced, and i wonder how to start dealing with this design problem.
What i think ...
- i would use bipolar CML invertors
- i would load the outputs of the invertors with 2 known caps + input of next...
Hello,
I'm reading a book on oscillator design. First they analyse the open-loop system, then they talk about phase/amplitude mismatch. You're peak in magnitude not corresponding to your phase. They suggest different oscillator architectures and there suddenly the term "high loaded Q". Could...
Thanks for your input!
I'm not very familiar with verilog A neither, I have no idea how to do this. If someone would have a suggestion, this would be greatly appreciated
Verilog doesn't like abrupt discontinuities neither, Verilog A is interpreted by Spectre here. Normally one could give...
Hello,
thanks for your reply.
I tried this implementation before asking for help but it doesn't work. The output is clipped to some max and min indeed, but the integration function seems to work with some internal variable which is not clipped. Imagine i apply some positive voltage. Output...
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