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Hi guys,
I'm new to pipeline ADC.
Now I'm confused about the residue amplifier.
Based on the system function block,the Vout vs Vin for every stage,
should be:Vout=2^B*(Vin-VDAC),
(B is the number of bit of every stage,VDAC is the voltage from B+1 bit DAC).
But in the realization of the...
Hi guys,
I'm new to pipeline ADC.
Now I'm confused about the residue amplifier.
Based on the system function block,the Vout vs Vin for every stage,
should be:Vout=2^B*(Vin-VDAC),
(B is the number of bit of every stage,VDAC is the voltage from B+1 bit DAC).
But in the realization of the residue...
Hi all:
Now I am working on the simulation of the whole chip(a buck dc-dc) using the star-hspice,I came across a problem that the simulation file is so big(usually >1Gb),I have used the ".option probe" to save the point I need to investigate,but still the file is large,I remember that...
hi harrytrinh:
I know I need a regulator(<5v output) as my internal supply for the inner circuit.But have you ever considered that how much the bandwidth of the regulator,and how big is the cap you will put at the output of the regulator,and you should guarantee that when switching,the...
Hi guys:
I am just getting involved in a DC-DC project,since the input voltage is high than 15V and our process is about 5v cmos process,so I need to design a inner regulator as a supply for the circuit.
But for the regulator,I don't know how to decide its specification,such as...
Hi guys:
Now I need to design a DC-DC converter,switching frequency is 1Mhz,and I have read AI.Pressman's <Switching power supply design> ,and it seems to me that the book focus on the voltage-mode doing a lot of analysis on the voltage mode stability.But what about the current-mode,since the...
Hi guys:
Now I need to design a DC-DC converter,switching frequency is 1Mhz,and I have read AI.Pressman's <Switching power supply design> ,and it seems to me that the book focus on the voltage-mode doing a lot of analysis on the voltage mode stability.But what about the...
ldo heavy load
hi guys:
As an classical LDO,comprised by three stage:an high gain stage,a buffer stage and a output stage.A big cap is at the output and the esr is essential to the stability.
There are 2 poles and 1 zero in the loop.My question is when the loading is changing and the 2 poles...
u can refer to the ieee paper "a_capacitor-free_cmos_low-dropout_regulator".
It gives u a general image about the conventional ldo,and proposes a damping method to stabilize the ldo.
Hope it will help~~
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