Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Thank you. I got the difefrence between ATPG and BIST.
But when we do RAM sequential ATPG , we do write to atleast one memory location and scanout the data to ensure address , data pins and control pins toggle. I understand RAM sequential for single port memory. is there any difference between...
If I understand your question correctly , it is the bypass mode and compression mode you are talking about.
Bypass mode is used usually during debugging any simulation failures. especially when chain test is failing in compression mode. In compression mode serial simulation failure debug...
How can we take care of testing dual port memory during ATPG? As far as I know dual port memories will be tested with custom alogorithm using BIST, so just eager to know how it is done during ATPG?
Hi,
I have read a statement on compression ratio that, effective compression will be less than chain:channel ratio . That means if I have generated EDT logic with chain:channel ratio of 10, I might get around 9.5. Please let me know the reason for actual reduction in compression.
generally how much coverage improvement can we expect from this? and also test pattern generation time should be more for ram_sequential mode. Please clarify .
Hi,
What does shadow logic around the memory mean? Does this include the muxes for selcting functional or bist mode signals ? I need to understand more on this and testing shadow logic.
From the above explaination I can conclude that if we need good coverage >99% stuck-at can fulfil it at slower frequency.
When we want to test with in a certain time frame(at-speed) for the node transition , we can go for atspeed testing, eventhough we might not be able to reach coverage of...
Thank you. Could you please explain more on "ATPG model should defined the possible fault for the std cells".
As far as I understand, ATPG model will have the functionality of a perticular std cell. How it takes acre of defining fault in ATPG model ?
Hi,
Please help me to understand , if there a need to run stuck-at fault model, after running transition fault model? are the stuck-at faults also covered by transition fault model ?
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
