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Recent content by naught

  1. N

    How to calculate the ideal agc threshold?

    To use AGC, I calculate the average received signal power as Pavg. And Pavg has to be compared with the pre-defined ideal AGC threshold, Pth. I want to know how Pth is calculated. My colleague calculate Pth this way: suppose both transmitter and receiver are using the same resolution DAC and...
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    What is written into FLASH really when using MCS file?

    basically I'm getting rid of the start colon mark, address, length infomation, type, and check sum in each line of the MCS file. Take the format above for example, even though there're data in the first line...I don't write any of it into Flash, because its "type" is not data. Neither do I...
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    What is written into FLASH really when using MCS file?

    thanks for the comfirmation. Now I'm combining every 2 ascii characters in the raw data section into one hex byte, then write it to FLASH.
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    What is written into FLASH really when using MCS file?

    I'm doing a project of remote programming the FPGA, basically I have to write MCS file into flash without using JTAG. Now I've known that MCS file has its own structure, like head, address, type, checksum, and also contains a ASCII representation of the original bitstream contents(two ASCII...
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    help on the transmitting power in the air.

    I've been trying to run simulations in a cell-mobile scenario and the Shannon formula is used here. To use to the Shannon formula, I have to know the transmitting signal power which could help calculate the SNR. I've ready had the channel model. So the only remaining problem is the transmitting...
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    matrix inverse in vhdl

    if the matrix A is full rank, A could be represented in the form of A = L.*U, it's called LU decomposition. https://en.wikipedia.org/wiki/LU_decomposition then the inverse of A is A- = U- * L-.
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    quantization and how to determine the fixed point bit?

    Number A is the input of the system, let's assume it's 0.123456. After the double precision number A has been processed in the system, I get the double precision result B(the actual result). To get where my fixed point is, I apply the following procedure: the final form is Q1.(N-1), which...
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    [SOLVED] Synchronous clock division

    My bad... please delete this post. process(reset,clk) begin if reset='1' then qtemp <= 0; q1 <= '0'; elsif clk='1' and clk'event then if qtemp = 7999 then qtemp <= 0; q1 <= '1'; -- clock enable (tick) else...
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    sampling frequency in LTE&OFDM downlink.

    yes, sample rate, that's what baffles me so long! I come to know that the when the subcarrier space of OFDM is 15Khz, the OFDM signal lasts for 1/15K second. Now I'm going to to represent the OFDM signal by using 2048 subcarrier within the "1/15K second", then the interval between each...
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    sampling frequency in LTE&OFDM downlink.

    Re: sampling frequency in LTE&amp;OFDM downlink. rcdaniels, thanks for your help. In the 5 Mhz case, you point out that the effective bandwidth is now 0.59*7.68 MHz = 4.53 MHz. The 7.68 Mhz = (512 subcarrier) * (15 KHz subcarrier space). This 7.68Mhz is the bandwidth but it coincides with the...
  11. N

    sampling frequency in LTE&OFDM downlink.

    I want to determine the system clock frequency under which my Fpga program is working. I assume the bandwidth = subcarrier number * subcarrier space, and the subcarrier numuber equals the ifft number so the bandwidth = ifft number * subcarrier space, 7.68MHZ = 512 * 15KHZ. bandwidth =...
  12. N

    Using "initial" for my FPGA programming

    maybe you want to try add "reset" signal in your always. something like always(clk,rst) if(rst) state <= idle; else if(posedge(clk)) case:
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    [SOLVED] Help with Xilinx ifft ipcore.

    I was worried that if I include too many signals to be reset in the condition " rst = '1' "...it might cause too much burden, so I disperse signals to other cases to be reset, of course before these signals are used. I guess this does have some problems... anyhow, at least I know where to...
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    [SOLVED] Help with Xilinx ifft ipcore.

    I find the problem...so silly!!! when rst = '1', the value of start_ifft is not defined, which cause the rfd_rx1 to be uncertain. the wrong code: process(clk,rst) begin if(rst = '1') then pr_state <= s0; cnt3584 <= 0; addr2048 <= 0; addra_ram14336 <= 0; elsif(rising_edge(clk))...
  15. N

    [SOLVED] Help with Xilinx ifft ipcore.

    I have 7 frames to do the ifft calculation, each frame containing 512 data. Then each 512 is interpolated by 3*512 zeros. So now each frame is 2048 data. I choose the continuous pipeline way, but the first frame out of the ipcore is X`s. please help me identify where my problem is. I`ve been...

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