[SOLVED] Help with Xilinx ifft ipcore.

[naught]

I have 7 frames to do the ifft calculation, each frame containing 512 data. Then each 512 is interpolated by 3*512 zeros. So now each frame is 2048 data.

I choose the continuous pipeline way, but the first frame out of the ipcore is X`s. please help me identify where my problem is. I`ve been stuck here the whole day.


there are 7 edone and done impulse, indicating that 7 frames processed.
the dv signal is data valid.
you can see the first 2048 data is X`s.



rfd_rx1 is ready for data, I choose 3 clock offset way, so data_in is 3 clock later after rfd_rx1.
the data_in are doutb_ram14336_rx1 and doutb_ram14336_rx3.



xk_index is the number of the output data. when xk_index = 0, there is data. but after that there is problem.


here`s how I declare the ipcore.

---

Code VHDL - [expand]
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ifft_rx1 : ifft2048
  PORT MAP (
    clk => clk,  -- 20Mhz
    sclr  => rst,
    start => start_ifft,
    xn_re => doutb_ram14336_rx1,
    xn_im => doutb_ram14336_rx3,
    fwd_inv => '0',  -- inverse fft
    fwd_inv_we => '1',
    rfd => rfd_rx1,
    xn_index => xn_index,
    busy => busy,
    edone => edone,
    done => done,
    dv => dv,
    xk_index => xk_index,
    xk_re => xk_re_rx1,  
    xk_im => xk_re_rx3   
  );

---

it looks to me that only the first 2048 data is not working, the rest 6*2048 ifft phase is working...put aside its accuracy for a moment.

the modelsim warning is "# ** Warning: There is an 'U'|'X'|'W'|'Z'|'-' in an arithmetic operand, the result will be 'X'(es)."
this warning happens between around 1,000,000ns and 1,107,446ns, the area between the 2 yellow vertical line.
It`s the phase where the first 2048 data just finished loaded into the ifft core, where the 2nd 2048 data is getting loaded.
the second vertical yellow line is where the ifft core starts output.


please help...

 

[naught]

I find the problem...so silly!!!
when rst = '1', the value of start_ifft is not defined, which cause the rfd_rx1 to be uncertain.
the wrong code:

---

Code VHDL - [expand]
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process(clk,rst)
    begin
        if(rst = '1') then
            pr_state <= s0;
            cnt3584 <= 0;
            addr2048 <= 0;
            addra_ram14336 <= 0;
        elsif(rising_edge(clk)) then
            case pr_state is
                when s0 =>
                    if(start = '1') then
                        pr_state <= s1;
                    else
                        pr_state <= s0;
                    end if;
                    ena_ram3584 <= '0';
                    wea_ream3584 <= "0";
                    ena_ram14336 <= '0';
                    wea_ram14336 <= "0";
                    enb_ram14336 <= '0';
                    start_ifft <= '0';

---

simply add "start_ifft <= '0';" to the if rst = '1' condition. then the module works.
the right code:

---

Code VHDL - [expand]
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process(clk,rst)
    begin
        if(rst = '1') then
                        start_ifft <= '0';
            pr_state <= s0;
            cnt3584 <= 0;
            addr2048 <= 0;
            addra_ram14336 <= 0;
        elsif(rising_edge(clk)) then
            case pr_state is
                when s0 =>
                    if(start = '1') then
                        pr_state <= s1;
                    else
                        pr_state <= s0;
                    end if;
                    ena_ram3584 <= '0';
                    wea_ream3584 <= "0";
                    ena_ram14336 <= '0';
                    wea_ram14336 <= "0";
                    enb_ram14336 <= '0';
                    start_ifft <= '0';

---

--------------------------------------------------------------
though it works, this is still confusing. the datasheet does not specify the start_ifft signal shall be set to 0 from the very beginning.
even if I did not set it to 0 from the beginning, I have set it to be 0 at pr_state = s0....why wouldn`t this work...

 

[TrickyDicky]

I guess not all of the signals get reset, so if they hold their value through other states, because nothing has been set for the signals values, they initialise to 'U'

 

[naught]

I was worried that if I include too many signals to be reset in the condition " rst = '1' "...it might cause too much burden, so I disperse signals to other cases to be reset, of course before these signals are used.
I guess this does have some problems... anyhow, at least I know where to look for errors should it happen again..

thanks for your help TrickyDicky.