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Hi,
I am using defparam to modify the parameter inside the generate statement. But DC compiler gives me error. The generate statement has 2x2 array.
Could any one suggest some solution.
Thanks,
natwar
Hi,
I am using `define MEM_RST in the memory which basically use reset if MEM_RST is defined. While compiling using design compiler I defined MEM_RST in the top file only . But it does take into effect. Is there a way I can do systhesis without defining MEM_RST for each file where it is used...
I tried read_verilog for my design hierarchy. But read_verilog could not refer or resolve the module instances used in my top design. But if I use analyze followed by elaborate I see no issue. So, I wonder what is the need to use read_verilog in the first place?
Thanks,
Natwar
Hi ,
I am using synopsys design vision. I want to synthesize my design and write the output format into EDIF. But design vision gives an error that it cannot be done in XG mode.
Could you please help me regarding this.
Natwar
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