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verilog single file format is supported with older versio of TMAX like D 2010.*
You can write out verilog reading in the stil test vector from TMAX. The written out verilog will be inclusive of the test patterns.
Hi,
Can somebody suggest a waveform debugger which can handle data of around 10 GB.. at least
I'm using dve where I'm having a really tough time handling huge databases . . even with 10 CPU machines
~Nandasan
StdCell libraries may be foundry specific as well as company specific ..
The StdCell (gates) are designed by several companies for their own usage .. but the devices being used ( pmos/nmos transistors ) to draw the schematics & layouts eventually come from the foundry always . .
Different...
What methodology do you adopt when you have an IP with scan (no compression) and you have to integrate this with the top level scan logic using compression and OCC ?? What is the best way to go about converging on the compression ratio in this case ??
~Nandasan
Re: Digital logic design
You need to decide the width depending upon the correlation between the rise, time fall time and propagation delay of the inverter for multiple drive strengths.
You should be narrowing down the margin between rise and fall time .. ( difference if any should be in order...
I think if you have negative edge flops talking to positive edge ones, then lockup latches should be automatically inserted by the synthesizing tool to prevent data shift through both the flops in one clock cycle. This will precisely prevent the hold violation the capture flop.
Are you using two different sessions for scan shift and scan capture in STA ?? You must be using a case analysis on the scan enable accordingly??
There may be multiple reason that its failing... Check the clock waveform timing first in STA session using report_clocks .. compare the duty cycle...
Re: [High-Vt, Low-Vt] Mix library synthesis -> what approach is better?
You need to decide the trick of the trade depending on your requirements. If you highly leaky design better go for all HVT and if you have a timing critical design where you can compromise a bit on the leakage go for LVT...
When you're linking your design after compilation & elaboration DC uses the link library which being empty in first case Errors out.
Don't you have any StdCells that you're saying that you need only 1 lib here. Target lib will mainly comprise of StdCells . Link lib will comprise of structural...
Re: WLM: Transition or Propagation Delay
NLDM models are dumb with respect to timing. Mainly used in crude synthesis .
use should use ccs models for timing instead.
Wire load model will give you the net delays and gate delays from which the tool would derive the stage delays...
Transition...
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