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hehe... :-D I'm not an engineer.. I'm more to programmer at high level language. Debugging code at higher languages like java, and python much easier.. I thought VHDL is like any other programming languages that I learned before, that why I took the subject this semester... After this project, I...
Hi, Does you mean change this code
if full_empty = "10" then NEXT_STATE <= S1;
into this
if full_empty = "01" then NEXT_STATE <= S1;
??
I changed it but same error happen.. Furthermore, does it compulsory for me to do the simulation in ModelSim?
Hi Everyone,
I'm making an asynchronous pipeline which mean every stage of pipeline control by local controller, using Quartus 2, written in VHDL language. The problem i'm facing is unversity waveform program shown that the data is not transferred between stages as shown in below images. Below...
Hi Std_match and ads_ee,
thank you for your guidance.. Actually I'm doing my final year project whereby I want to compare mousetrap and gasp pipeline. For mousetrap, I got no issue since its simple, in other hand, Gasp pipeline really give me headache.
Hi, actually I want to make a controller which will enable the latch.
As you can seen on my updated code below, the signal en will take the output from w AND x to enable the latch. After that, w and x will fetch the en. For example, initially, let say the w and x values start at 1, the en will...
Problem in Gasp Pipeline Controller in VHDL
Hi everyone,
I'm working on the Gasp Controller as shown within the red area in the image attachment 111734. I did the code but the problem is the result didn't display as what show in the below image. Could anyone please advice/assist on this...
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