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Hello everyone :)
I need to modify the XOR operations used in the parity calculation in such a way that the XOR gates described are each supplemented by a hold time and the propagation delay and use the circuit diagram as a guide.
For the duration of the hold time, the signal used should...
Here an implementation whitout using any mux, maybe it will help someone in the future :)
-- bidirektionale shift register mit data-load und serielle(R/L) output mit D-ff
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port( din: in std_logic_vector(3 downto 0)...
Thanks a lot for your answer !
I did try another way but this time I'm not getting my dout updated when there is a shift. any idea how to fix it ?
library ieee;
use ieee.std_logic_1164.all;
entity bi_shiftReg_ff is
port( din: in std_logic_vector(3 downto 0);
set, n_reset: in...
Hello everyone,
So I'm trying to implement a shift R/L register using a d_ff component (asynchronous low active reset, asynchronous set), but I'm getting this error
Can you tell me please what I'm doing wrong and how I can fix it ? Thank you in advance for your help
Here the code for the d_FF...
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