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Hi,
How do we determine DC gain requirement for a pipelined ADC. I was reading on some papers that it depends on the resolution of the converter. According to the equation
A > 2^N
Where A is the DC gain and N is the resolution of the converter. So , for a 8-bit ADC, minimum required DC gain...
Thank You for the response. No it is a Pipeline ADC. What I understood is that each stage gives a valid digital output after one clock cycle. During first half of the clock cycle Sampling will take place. During the second half digitization will take place.
Please correct me if I am wrong.
I am designing a 10-bit pipeline ADC. I have a very basic question about the ADC. I have read in some paper that for a 10-bit pipeline ADC, 6 initial clock cycles are required before the first digital outcome becomes valid. Can some one please tell me how its 6 initial clock cycles required...
Dear All,
I have designed a fully differential operational amplifier with Continuous time common mode feedback circuit. Now I want to check if the CMFB circuit is stable or not. I already tested my operational amplifier in differential mode and it is stable using the AC analysis. Can anyone...
Dear All,
As we know that from theory in a Pipelined ADC each stage must be settled within half of the clock period. Say, the ADC I am designing has a sampling frequency of 50MSPs which equals a period of 20 nS. So theoretically each stage must be settled within 10 nS i.e. in less then half of...
Can you please explain a little bit which stages you're talking about as it is a 3-bit flash ADC. And how can I run INL analyses vs. temperature and corners ? I also know how to plot INL/DNL for my ADC.
regards
Dear erikl
Attached are the libraries I use which are standard for umc 130nm. Do I need to disable any of the model library while doing the corner simulation ?
So what youre saying is that I should do corner simulation with five different sections, doing corner simulation of each section...
Dear Erikl
Any tutorial you recommend to do this. And how I choose sigma. Like in my current mc simulation I ma chossing sigma = 3.
And how can I know which model libraries should I include for umc130nm technology for the corner simulation you mentioned above. ?
Regards
Dear erikl
Alright . I will do the simulation with the corner libs and get back to you with the results. One more thing.
The procedure is same as montecarlo or its different. As in my monte carlo simulation what I did is first I included the model library as mentioned in my previous post on my...
Dear erikl
In my previous simulation I did monte carlo simulation of the same circuit for only process variations with 5 runs. This time I did it for both process and mismatch.
As you said in you post
What you mean is over the corner simulation , process and mismatch variation , my ADC won't...
Dear Erikl
Here is the monte carlo simulation for both process and mismatch variation for a 3-bit flash ADC. What do you conclude from this plot ?
Library I am using is L130E_HS12_V241_MC_CORNER.lib.scs
regards
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