Pipelined ADC settling time

[musclesinwood]

Dear All,

As we know that from theory in a Pipelined ADC each stage must be settled within half of the clock period. Say, the ADC I am designing has a sampling frequency of 50MSPs which equals a period of 20 nS. So theoretically each stage must be settled within 10 nS i.e. in less then half of the clock cycle. I thought a lot about it but did not understand it completely. How can I make sure that each stage has been settled within half of the clock cycle ? How can I test it ?

Regards

 

[dick_freebird]

Generally in simulation, with as much parasitic realism as
you can muster. ADC testing for anything high-bit-count
is tough, seems to be a lot of post-processing of bit-code
output using statistics because it's so tough to get reliably
clean inputs with all the switching activity. And you don't
get to poke the guts of a finished chip design, except at
the FA lab when things don't quite work out as planned.