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Okay thank you for that.
I know what I want to base it on, so I want to use something like
IF (Fire'event AND Fire = '1') THEN
......
ComputationReady = '1';
How do I then set the delay I want? In this case it's 4 cycles. I assume using any timing is useless outside of simulation. So I need...
I'm using VHDL and I want to introduce a delay before assigning two signals to being equal. My thinking is of a switch, that moves from all zeros or null to the wire I want to take the signal from after x amount of clk_cycles. Is this possible? My issue is that my design is outputting junk data...
I am having a little trouble when compiling. I am getting the following error:
"Type conversion (to ieee.numeric_std.unsigned) conflicts with expected type std.standard.integer"
From the following
TYPE Mem IS ARRAY ( AddressSize DOWNTO 0) of std_logic_vector (7 DOWNTO 0);
SIGNAL Memory ...
I am attempting to create a simple block of hardware, that takes 3 inputs (a, b and c) and outputs a*b + c.
Assuming the inputs are all 8 bit, and the output will need to be 16 bit I have created this code.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
ENTITY...
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