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Recent content by msaadrahman

  1. M

    help me in graduation project

    Which operating system do you plan to use? -Saad Rahman
  2. M

    pc based oscilloscpe , circuit is connected by parallel por

    Re: pc based oscilloscpe - help needed Have you developed your own software to get output on the PC or are you using a FPGA based solution? I know of a lot of implementations in which a signal is fed into a FPGA and it displays the output on a PC. The main issue with those is to get the...
  3. M

    how to learn orcad sofware

    Hi, I do not know which version you are using since you did not mention it but here are a few links which might be useful to you: **broken link removed** **broken link removed** https://www.ece.rice.edu/~jdw/orcad/OrCAD_Tutorial/docs/tutorial.pdf Regards, Saad Rahman
  4. M

    CMOS DIGITAL INTEGRATED BOOKS

    A good place to find many of the online Webcast's have been compiled on my Blog on the following link: https://saadrahman.wordpress.com/2010/02/04/webcast-resources/ Do check them out. Regards, Saad Rahman
  5. M

    Looking for Thesis on ASIC design

    Re: thesis on asic ASIC is quite a large field. What exactly do you wish to target? -Saad Rahman
  6. M

    INTRINSIC DELAY ? FAN OUT DELAY ?

    Intrinsic delay, is the delay with no output loading. Ref: Pg 428. Rabaey, Chandrakasan & Nikolic "Digital Integrated Circuits - A design perspective" - 2nd Edition. Regards, Saad Rahman
  7. M

    Need help in finding a project

    Hi, What kind of projects? You want to write some kind of VHDL code to design a DSP, or you want to do a project based around a DSP Processor? Regards, Saad Rahman
  8. M

    Looking for ASIC design software

    Re: Help me out Hi, I think if you are planning on doing a custom layout than you would definetly be using Cadence Vitruso. For Synthesis - Synopsys Design Compiler (Design Vision) For Place & Route - SoC Encounter or Silicon Ensemble Hope this helps. If you need any further answers do...
  9. M

    Which branch of Electronics is most profitable ?

    Re: Beginner Hi, I think the following link should be able to provide you some answers for your questions: **broken link removed** Regards, Saad Rahman
  10. M

    The Bubble Error Correction Circuitry behavior

    Re: adc converter The outputs of the comparator should be a thermometer code with a single transition. However, sometimes a lone 1 will occur within the strings of 0s (or a 0 within the strings of 1s) due to comparator metastability, noise, cross talk, limited bandwidth, etc. These bubbles...
  11. M

    CMOS ???? CMOS PARASITICS ?

    Hi, Incase you have the book "Digital Integrated Circuits" by Jan Rabaey & Chandrakasan & Borivoje you can refer on Page 137. Otherwise this might be a little useful as well: https://en.wikipedia.org/wiki/Parasitic_capacitance Regards, Saad Rahman
  12. M

    How to design ADC converter and how it recognizes incoming signals?

    adc converter Hi, It depends on what architecture you want to use. But a simple way for designing an ADC you need a Comparator, than you need Bubble Error Correction Circuitry and afterwards you need a ROM Encoder to convert the thermometer code to Binary Code. And than you are more or less...
  13. M

    structured asic design tools

    Hi, I assume you mean a RTL-> GDSII flow. In that case you need Modelsim to write your code in VHDL, for synthesis you can use Synopsys tools which will map the libraries according to the process that you are going to use for the chip tapeout. After Synthesis the tool will generate a .v file...
  14. M

    Pads for Digital and Analog

    Well I found some answers to my last questions which are posted below. If some one could further verify their utility it would be nice. BU1P - buffer for signals (Digital Part) **broken link removed** GND3ALLP - (GND for Digital Part) **broken link removed** VDD3ALLP - (VDD for Digital Part)...
  15. M

    Gate count per square mm

    "To effectively implement high-complexity designs, access to leadership design implementation capabilities is crucial, and without being able to implement high gate count designs, the value of internal wafer fab facilities and leadership process technologies is limited." Ref: (Page 59)...

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