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I was wondering what will be a better placement for the current shunt resistor between the two diagrams shown below.
- Gate drivers and all other analogue sub-parts are ground referenced.
We need to assemble 65W laptop chargers for small to mid volume production (around 1000 units per month). The PCB has both SMD and through hole components. SMD on the bottom layer and through hole on the top layer. I was wondering what is the standard method for assembling through hole and...
I found out the problem.
Majority of the loss is coming from high amount of ripple current circulating between the decoupling capacitors and the cable inductance of power cable connecting 12V source to the PCB. (Measured 1.5uH using LCR meter)
Strategic placement of capacitors on the PCB...
Hi thanks everyone for the reply.
After all the suggestions, I tried to see the effect of probing. In the protos of the previous post VDS was measured using a HV differential probe and inductor current using a normal passive probe.
I made three measurements:
1. Measure current with differential...
I have a tied an RL load to a 12V H-Bridge operating in a usual fashion where alternate FETs are ON followed by a large dead time where all FETs are OFF and then the adjacent pair of FETs are turned ON and the cycle repeats.
L = 32uH wound on gapped ferrite core.
R = 0.25 Ohm
To sense the...
I am testing a 12V full bridge converter connected to a step up transformer. The output of the transformer is rectified using a SiC bridge diode. There's no inductor between the SiC output and the bulk capacitor.
The transformer is being driven by simple PWM. Alternate high and low FETs are...
Hi, thanks for the reply.
I understand that RMS is what we should be talking about instead of average, but I think the error of approx 300% to 400% is too large to depend on RMS or average especially as the duty cycle approaches 100%.
- The current magnitude is different for different snapshots...
Thanks for the reply.
Here's the approximate loss calculation method I used.
Rds_on at Tj = 80C = 2.5mOhm max. Rise and fall time = 25ns approx. V_ds = 13V, I_Out = 40A avg. Based on this:
I^2R loss = 40x40x2.5m = 4W. But the switch is only active 50% time in full bridge so loss = 2W.
I am working on a 12V phase shifted full bridge connected to a 1:38 step-up transformer. The output of the transformer is rectified using SiC diode bridge. Fsw = 80KHz.
The MOSFET is PSMN2R030YLDX with 2mOhm resistance and maximum 2.5mOhm at Tj = 80C.
- When driving 40A current into the...
We have to design PFC with multiple power outputs ranging from 3KW to 10KW. Input voltage range 160V to 280V and output voltage = 400V. Up till now I have only designed and tested between 200W to 800W. I especially liked CrM topology over CCM, they simply run very smooth and cool.
1. Add ceramic decoupling capacitors close to the bridge
2. If the FETs still overshoot, add an RC snubber across each drain-source. A reasonable value to start with would be 1 Ohm in series with 4.7nF.
Just to share some experience, I've never actually had the need to use electrolytic capacitors for any buck converter at such frequencies.
And also, an X7R cap in 0805 package can easily handle over 3 amps of current. With a 1210 size cap, I will be expecting over 6A capability to begin with.
I think the beat effect will be even more severe at 80KHz followed by 70KHz, beating at 10KHz. If both the stages are at 80KHz then beat will be in order of a few 100Hz considering slight mismatch. But to beat at such low frequency the system should probably have a very low damping factor. It's...