Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Recent content by moh_monem43

  1. M

    Telecom Engineer looking for job

    Hi, I'm telecom engineer. I'm working in fiper optic network (SDH & DWDM) in saudi I'm looking for job in Canada or USA. can any one help me? any links to apply for job? Regards
  2. M

    nature of sun, solar system, space

    Re: nature of sun any answer??
  3. M

    nature of sun, solar system, space

    nature of sun hi, i need books talking about the sun - nature of sun- solar system,...... can any body help me. thx
  4. M

    I want to study CCNA - looking for books, advices etc.

    Re: I need study CCNA thank you very much joe1986 for your help.
  5. M

    I want to study CCNA - looking for books, advices etc.

    Re: I need study CCNA thank you joe1986, the_risk_master but the files not found.
  6. M

    I want to study CCNA - looking for books, advices etc.

    I need study CCNA Dear, I want study CCNA. How can i start? what is the best book? any advices? thanks alot.
  7. M

    what is the benefit of unsynthesizable code?

    unsynthesizable Dear, Some codes in VHDL are unsynthesizable. As i understand we can't apply on FPGA or CPLD. So what is the benefit of it? thanks.
  8. M

    how can i execute delay time??

    thx FrankCh for your concern but, how can i make additional timing constraints in @ltera software ??
  9. M

    laser signal to electrical signal?

    can i convert laser signal to electrical signal??
  10. M

    how can i execute delay time??

    How can I make simulation for inertial delay and transport delay? I tried to execute these examples Library ieee; Use ieee.std_logic_1164.all; Entity buf is Port (a : in std_logic; B : out std_logic); End buf; Architecture buf of buf is Begin b <= a after 20 ns; end buf; library...
  11. M

    VHDL or Verilog certification as CCNA in network

    Is there VHDL or Verilog certification as CCNA in network??
  12. M

    what is the program used for Xilinx FPGA?

    waht the program used for programming xilinx FPGA which equal quartusII in altera? and how can i down load? is it free? thanks
  13. M

    What are the differences between Labview and VHDL?

    Re: labview&VHDL this means i can't program CPLD&FPGA by labview??
  14. M

    What are the differences between Labview and VHDL?

    dear all, what is the different between labview and VHDL? what is the benefits of both? and which better?? thanks

Part and Inventory Search

Back
Top